| 146 |
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| 147 |
/* Interrupt vectors */ |
/* Interrupt vectors */ |
| 148 |
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| 149 |
#define SIG_INTERRUPT0 _VECTOR(1) |
/* External Interrupt Request 0 */ |
| 150 |
#define SIG_INTERRUPT1 _VECTOR(2) |
#define INT0_vect _VECTOR(1) |
| 151 |
#define SIG_INPUT_CAPTURE1 _VECTOR(3) |
#define SIG_INTERRUPT0 _VECTOR(1) |
| 152 |
#define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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| 153 |
#define SIG_OVERFLOW1 _VECTOR(5) |
/* External Interrupt Request 1 */ |
| 154 |
#define SIG_OVERFLOW0 _VECTOR(6) |
#define INT1_vect _VECTOR(2) |
| 155 |
#define SIG_UART_RECV _VECTOR(7) |
#define SIG_INTERRUPT1 _VECTOR(2) |
| 156 |
#define SIG_UART_DATA _VECTOR(8) |
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| 157 |
#define SIG_UART_TRANS _VECTOR(9) |
/* Timer/Counter1 Capture Event */ |
| 158 |
#define SIG_COMPARATOR _VECTOR(10) |
#define TIMER1_CAPT1_vect _VECTOR(3) |
| 159 |
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#define SIG_INPUT_CAPTURE1 _VECTOR(3) |
| 160 |
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| 161 |
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/* Timer/Counter1 Compare Match */ |
| 162 |
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#define TIMER1_COMP1_vect _VECTOR(4) |
| 163 |
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#define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
| 164 |
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| 165 |
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/* Timer/Counter1 Overflow */ |
| 166 |
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#define TIMER1_OVF1_vect _VECTOR(5) |
| 167 |
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#define SIG_OVERFLOW1 _VECTOR(5) |
| 168 |
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| 169 |
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/* Timer/Counter0 Overflow */ |
| 170 |
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#define TIMER0_OVF0_vect _VECTOR(6) |
| 171 |
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#define SIG_OVERFLOW0 _VECTOR(6) |
| 172 |
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| 173 |
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/* UART, Rx Complete */ |
| 174 |
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#define UART_RX_vect _VECTOR(7) |
| 175 |
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#define SIG_UART_RECV _VECTOR(7) |
| 176 |
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| 177 |
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/* UART Data Register Empty */ |
| 178 |
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#define UART_UDRE_vect _VECTOR(8) |
| 179 |
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#define SIG_UART_DATA _VECTOR(8) |
| 180 |
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| 181 |
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/* UART, Tx Complete */ |
| 182 |
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#define UART_TX_vect _VECTOR(9) |
| 183 |
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#define SIG_UART_TRANS _VECTOR(9) |
| 184 |
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| 185 |
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/* Analog Comparator */ |
| 186 |
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#define ANA_COMP_vect _VECTOR(10) |
| 187 |
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#define SIG_COMPARATOR _VECTOR(10) |
| 188 |
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| 189 |
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| 190 |
#define _VECTORS_SIZE 22 |
#define _VECTORS_SIZE 22 |
| 191 |
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