| 78 |
CPI rA3,0xFF |
CPI rA3,0xFF |
| 79 |
BREQ 2b ; no (unsigned overflow) -> signed underflow |
BREQ 2b ; no (unsigned overflow) -> signed underflow |
| 80 |
|
|
| 81 |
|
#ifdef __AVR_ENHANCED__ |
| 82 |
|
|
| 83 |
|
; this section of code is used by processors which have MUL instruction |
| 84 |
|
|
| 85 |
|
; now multiply mantissa A[rA2:rA1:rA0] * B[rB2:rB1:rB0] |
| 86 |
|
; result : [rr5:rr4:rr3:rr2:rr1:rr0] |
| 87 |
|
|
| 88 |
|
; definitions used by calculation |
| 89 |
|
#define rr2 rAE |
| 90 |
|
#define rr3 rTI1 |
| 91 |
|
#define rr4 rBE |
| 92 |
|
#define rr5 rB3 |
| 93 |
|
#define rmh r1 ; the multiply result high register |
| 94 |
|
#define rml r0 ; the multiply result low register |
| 95 |
|
|
| 96 |
|
MUL rA0, rB0 ; 0+0 = 0,1 |
| 97 |
|
MOV rr4, rmh ; rr1 == rr4 |
| 98 |
|
PUSH rml ; rr0 finished |
| 99 |
|
|
| 100 |
|
CLR rr2 |
| 101 |
|
MUL rA0, rB1 ; 0+1 = 1,2 |
| 102 |
|
ADD rr4, rml |
| 103 |
|
ADC rr2, rmh |
| 104 |
|
CLR rr3 |
| 105 |
|
MUL rA1, rB0 ; 1+0 = 1,2,3 |
| 106 |
|
ADD rr4, rml |
| 107 |
|
ADC rr2, rmh |
| 108 |
|
ADC rr3, rr3 |
| 109 |
|
PUSH rr4 ; rr1 finished |
| 110 |
|
|
| 111 |
|
CLR rr4 |
| 112 |
|
MUL rA0, rB2 ; 0+2 = 2,3 |
| 113 |
|
ADD rr2, rml |
| 114 |
|
ADC rr3, rmh |
| 115 |
|
MUL rA1, rB1 ; 1+1 = 2,3,4 |
| 116 |
|
ADD rr2, rml |
| 117 |
|
ADC rr3, rmh |
| 118 |
|
ADC rr4, rr4 |
| 119 |
|
CLR rA0 |
| 120 |
|
MUL rA2, rB0 ; 2+0 = 2,3,4 |
| 121 |
|
ADD rr2, rml |
| 122 |
|
ADC rr3, rmh |
| 123 |
|
ADC rr4, rA0 |
| 124 |
|
|
| 125 |
|
CLR rr5 |
| 126 |
|
MUL rA1, rB2 ; 1+2 = 3,4,5 |
| 127 |
|
ADD rr3, rml |
| 128 |
|
ADC rr4, rmh |
| 129 |
|
ADC rr5, rr5 |
| 130 |
|
MUL rA2, rB1 ; 2+1 = 3,4,5 |
| 131 |
|
ADD rr3, rml |
| 132 |
|
ADC rr4, rmh |
| 133 |
|
ADC rr5, rA0 |
| 134 |
|
|
| 135 |
|
MUL rA2, rB2 ; 2+2 = 4,5 |
| 136 |
|
ADD rr4, rml |
| 137 |
|
ADC rr5, rmh |
| 138 |
|
|
| 139 |
|
; converting result to original format |
| 140 |
|
MOV rA2, rr5 |
| 141 |
|
MOV rA1, rr4 |
| 142 |
|
MOV rA0, rr3 |
| 143 |
|
; rr2 is the right one, no need to move |
| 144 |
|
|
| 145 |
|
#undef rr5 |
| 146 |
|
#undef rr4 |
| 147 |
|
#undef rr3 |
| 148 |
|
; definitions used by result |
| 149 |
|
#define rr5 rA2 |
| 150 |
|
#define rr4 rA1 |
| 151 |
|
#define rr3 rA0 |
| 152 |
|
// #define rr2 rAE |
| 153 |
|
#define rr1 rT1c |
| 154 |
|
#define rr0 rT0 |
| 155 |
|
#define rb5 rTI1 |
| 156 |
|
#define rb4 rBE |
| 157 |
|
#define rb3 rB3 |
| 158 |
|
|
| 159 |
|
; take out the lowest bytes from stack |
| 160 |
|
POP rr1 |
| 161 |
|
POP rr0 |
| 162 |
|
; +++ 44 instructions +++ |
| 163 |
|
|
| 164 |
|
#else // __AVR_ENHANCED__ |
| 165 |
|
|
| 166 |
|
; this section of code is used by processors which have not MUL instruction |
| 167 |
|
|
| 168 |
; now multiply mantissa A[rA2:rA1:rA0] * B[rb5:rb4:rb3:rB2:rB1:rB0] |
; now multiply mantissa A[rA2:rA1:rA0] * B[rb5:rb4:rb3:rB2:rB1:rB0] |
| 169 |
; result : [rr5:rr4:rr3:rr2:rr1:rr0] |
; result : [rr5:rr4:rr3:rr2:rr1:rr0] |
| 170 |
#define loop rTI0 |
#define loop rTI0 |
| 236 |
adc rb5,rb5 |
adc rb5,rb5 |
| 237 |
TST loop |
TST loop |
| 238 |
BRNE 1b |
BRNE 1b |
| 239 |
|
; +++ 49 instructions +++ |
| 240 |
|
|
| 241 |
|
#endif // __AVR_ENHANCED__ |
| 242 |
|
|
| 243 |
|
|
| 244 |
; multiplication done : result in rr5:rr4:rr3:rr2:rr1:rr0 |
; multiplication done : result in rr5:rr4:rr3:rr2:rr1:rr0 |
| 245 |
; = rA2:rA1:rA0:rAE:rr1:rr0 |
; = rA2:rA1:rA0:rAE:rr1:rr0 |