| 1 |
/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */ |
| 2 |
/* |
| 3 |
Written 1996-1999 by Donald Becker. |
| 4 |
|
| 5 |
This software may be used and distributed according to the terms |
| 6 |
of the GNU Public License, incorporated herein by reference. |
| 7 |
|
| 8 |
This driver is for the 3Com "Vortex" and "Boomerang" series ethercards. |
| 9 |
Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597 |
| 10 |
and the EtherLink XL 3c900 and 3c905 cards. |
| 11 |
|
| 12 |
The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O |
| 13 |
Center of Excellence in Space Data and Information Sciences |
| 14 |
Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771 |
| 15 |
*/ |
| 16 |
|
| 17 |
static char *version = |
| 18 |
"3c59x.c:v0.99L 5/28/99 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/vortex.html\n"; |
| 19 |
|
| 20 |
/* "Knobs" that adjust features and parameters. */ |
| 21 |
/* Set the copy breakpoint for the copy-only-tiny-frames scheme. |
| 22 |
Setting to > 1512 effectively disables this feature. */ |
| 23 |
static const int rx_copybreak = 200; |
| 24 |
/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */ |
| 25 |
static const int mtu = 1500; |
| 26 |
/* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
| 27 |
static int max_interrupt_work = 20; |
| 28 |
|
| 29 |
/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */ |
| 30 |
#define vortex_debug debug |
| 31 |
#ifdef VORTEX_DEBUG |
| 32 |
static int vortex_debug = VORTEX_DEBUG; |
| 33 |
#else |
| 34 |
static int vortex_debug = 1; |
| 35 |
#endif |
| 36 |
|
| 37 |
/* Some values here only for performance evaluation and path-coverage |
| 38 |
debugging. */ |
| 39 |
static int rx_nocopy = 0, rx_copy = 0, queued_packet = 0, rx_csumhits; |
| 40 |
|
| 41 |
/* A few values that may be tweaked. */ |
| 42 |
/* Time in jiffies before concluding the transmitter is hung. */ |
| 43 |
#define TX_TIMEOUT (2*HZ) |
| 44 |
|
| 45 |
/* Keep the ring sizes a power of two for efficiency. */ |
| 46 |
#define TX_RING_SIZE 16 |
| 47 |
#define RX_RING_SIZE 32 |
| 48 |
#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
| 49 |
|
| 50 |
#ifndef __OPTIMIZE__ |
| 51 |
#warning You must compile this file with the correct options! |
| 52 |
#warning See the last lines of the source file. |
| 53 |
#error You must compile this driver with "-O". |
| 54 |
#endif |
| 55 |
|
| 56 |
#include <linux/config.h> |
| 57 |
#include <linux/version.h> |
| 58 |
#ifdef MODULE |
| 59 |
#ifdef MODVERSIONS |
| 60 |
#include <linux/modversions.h> |
| 61 |
#endif |
| 62 |
#include <linux/module.h> |
| 63 |
#else |
| 64 |
#define MOD_INC_USE_COUNT |
| 65 |
#define MOD_DEC_USE_COUNT |
| 66 |
#endif |
| 67 |
|
| 68 |
#include <linux/kernel.h> |
| 69 |
#include <linux/sched.h> |
| 70 |
#include <linux/string.h> |
| 71 |
#include <linux/timer.h> |
| 72 |
#include <linux/errno.h> |
| 73 |
#include <linux/in.h> |
| 74 |
#include <linux/ioport.h> |
| 75 |
#include <linux/malloc.h> |
| 76 |
#include <linux/interrupt.h> |
| 77 |
#include <linux/pci.h> |
| 78 |
#include <linux/netdevice.h> |
| 79 |
#include <linux/etherdevice.h> |
| 80 |
#include <linux/skbuff.h> |
| 81 |
#if LINUX_VERSION_CODE < 0x20155 |
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#include <linux/bios32.h> |
| 83 |
#endif |
| 84 |
#include <asm/irq.h> /* For NR_IRQS only. */ |
| 85 |
#include <asm/bitops.h> |
| 86 |
#include <asm/io.h> |
| 87 |
|
| 88 |
/* Kernel compatibility defines, some common to David Hinds' PCMCIA package. |
| 89 |
This is only in the support-all-kernels source code. */ |
| 90 |
|
| 91 |
#define RUN_AT(x) (jiffies + (x)) |
| 92 |
|
| 93 |
#include <linux/delay.h> |
| 94 |
|
| 95 |
#if (LINUX_VERSION_CODE >= 0x20100) |
| 96 |
char kernel_version[] = UTS_RELEASE; |
| 97 |
#else |
| 98 |
#ifndef __alpha__ |
| 99 |
#define ioremap(a,b) \ |
| 100 |
(((a)<0x100000) ? (void *)((u_long)(a)) : vremap(a,b)) |
| 101 |
#define iounmap(v) \ |
| 102 |
do { if ((u_long)(v) > 0x100000) vfree(v); } while (0) |
| 103 |
#endif |
| 104 |
#endif |
| 105 |
#if LINUX_VERSION_CODE <= 0x20139 |
| 106 |
#define net_device_stats enet_statistics |
| 107 |
#define NETSTATS_VER2 |
| 108 |
#endif |
| 109 |
#if LINUX_VERSION_CODE < 0x20138 |
| 110 |
#define test_and_set_bit(val, addr) set_bit(val, addr) |
| 111 |
#define le32_to_cpu(val) (val) |
| 112 |
#define cpu_to_le32(val) (val) |
| 113 |
#endif |
| 114 |
#if LINUX_VERSION_CODE < 0x20155 |
| 115 |
#define PCI_SUPPORT_VER1 |
| 116 |
#else |
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#define PCI_SUPPORT_VER2 |
| 118 |
#endif |
| 119 |
#if LINUX_VERSION_CODE < 0x20159 |
| 120 |
#define DEV_FREE_SKB(skb) dev_kfree_skb (skb, FREE_WRITE); |
| 121 |
#else /* Grrr, incompatible changes should change the name. */ |
| 122 |
#define DEV_FREE_SKB(skb) dev_kfree_skb(skb); |
| 123 |
#endif |
| 124 |
#if ! defined(CAP_NET_ADMIN) |
| 125 |
#define capable(CAP_XXX) (suser()) |
| 126 |
#endif |
| 127 |
|
| 128 |
#if defined(MODULE) && LINUX_VERSION_CODE > 0x20115 |
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MODULE_AUTHOR("Donald Becker <becker@cesdis.gsfc.nasa.gov>"); |
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MODULE_DESCRIPTION("3Com 3c590/3c900 series Vortex/Boomerang driver"); |
| 131 |
MODULE_PARM(debug, "i"); |
| 132 |
MODULE_PARM(options, "1-" __MODULE_STRING(8) "i"); |
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MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i"); |
| 134 |
MODULE_PARM(rx_copybreak, "i"); |
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MODULE_PARM(max_interrupt_work, "i"); |
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MODULE_PARM(compaq_ioaddr, "i"); |
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MODULE_PARM(compaq_irq, "i"); |
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MODULE_PARM(compaq_device_id, "i"); |
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#endif |
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|
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/* Operational parameter that usually are not changed. */ |
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|
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/* The Vortex size is twice that of the original EtherLinkIII series: the |
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runtime register window, window 1, is now always mapped in. |
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The Boomerang size is twice as large as the Vortex -- it has additional |
| 146 |
bus master control registers. */ |
| 147 |
#define VORTEX_TOTAL_SIZE 0x20 |
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#define BOOMERANG_TOTAL_SIZE 0x40 |
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|
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/* Set iff a MII transceiver on any interface requires mdio preamble. |
| 151 |
This only set with the original DP83840 on older 3c905 boards, so the extra |
| 152 |
code size of a per-interface flag is not worthwhile. */ |
| 153 |
static char mii_preamble_required = 0; |
| 154 |
|
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/* |
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Theory of Operation |
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|
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I. Board Compatibility |
| 159 |
|
| 160 |
This device driver is designed for the 3Com FastEtherLink and FastEtherLink |
| 161 |
XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs |
| 162 |
versions of the FastEtherLink cards. The supported product IDs are |
| 163 |
3c590, 3c592, 3c595, 3c597, 3c900, 3c905 |
| 164 |
|
| 165 |
The related ISA 3c515 is supported with a separate driver, 3c515.c, included |
| 166 |
with the kernel source or available from |
| 167 |
cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html |
| 168 |
|
| 169 |
II. Board-specific settings |
| 170 |
|
| 171 |
PCI bus devices are configured by the system at boot time, so no jumpers |
| 172 |
need to be set on the board. The system BIOS should be set to assign the |
| 173 |
PCI INTA signal to an otherwise unused system IRQ line. |
| 174 |
|
| 175 |
The EEPROM settings for media type and forced-full-duplex are observed. |
| 176 |
The EEPROM media type should be left at the default "autoselect" unless using |
| 177 |
10base2 or AUI connections which cannot be reliably detected. |
| 178 |
|
| 179 |
III. Driver operation |
| 180 |
|
| 181 |
The 3c59x series use an interface that's very similar to the previous 3c5x9 |
| 182 |
series. The primary interface is two programmed-I/O FIFOs, with an |
| 183 |
alternate single-contiguous-region bus-master transfer (see next). |
| 184 |
|
| 185 |
The 3c900 "Boomerang" series uses a full-bus-master interface with separate |
| 186 |
lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet, |
| 187 |
DEC Tulip and Intel Speedo3. The first chip version retains a compatible |
| 188 |
programmed-I/O interface that has been removed in 'B' and subsequent board |
| 189 |
revisions. |
| 190 |
|
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One extension that is advertised in a very large font is that the adapters |
| 192 |
are capable of being bus masters. On the Vortex chip this capability was |
| 193 |
only for a single contiguous region making it far less useful than the full |
| 194 |
bus master capability. There is a significant performance impact of taking |
| 195 |
an extra interrupt or polling for the completion of each transfer, as well |
| 196 |
as difficulty sharing the single transfer engine between the transmit and |
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receive threads. Using DMA transfers is a win only with large blocks or |
| 198 |
with the flawed versions of the Intel Orion motherboard PCI controller. |
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|
| 200 |
The Boomerang chip's full-bus-master interface is useful, and has the |
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currently-unused advantages over other similar chips that queued transmit |
| 202 |
packets may be reordered and receive buffer groups are associated with a |
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single frame. |
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|
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With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme. |
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Rather than a fixed intermediate receive buffer, this scheme allocates |
| 207 |
full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as |
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the copying breakpoint: it is chosen to trade-off the memory wasted by |
| 209 |
passing the full-sized skbuff to the queue layer for all frames vs. the |
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copying cost of copying a frame to a correctly-sized skbuff. |
| 211 |
|
| 212 |
|
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IIIC. Synchronization |
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The driver runs as two independent, single-threaded flows of control. One |
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is the send-packet routine, which enforces single-threaded use by the |
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dev->tbusy flag. The other thread is the interrupt handler, which is single |
| 217 |
threaded by the hardware and other software. |
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|
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IV. Notes |
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|
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Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development |
| 222 |
3c590, 3c595, and 3c900 boards. |
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The name "Vortex" is the internal 3Com project name for the PCI ASIC, and |
| 224 |
the EISA version is called "Demon". According to Terry these names come |
| 225 |
from rides at the local amusement park. |
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|
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The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes! |
| 228 |
This driver only supports ethernet packets because of the skbuff allocation |
| 229 |
limit of 4K. |
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*/ |
| 231 |
|
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/* This table drives the PCI probe routines. It's mostly boilerplate in all |
| 233 |
of the drivers, and will likely be provided by some future kernel. |
| 234 |
*/ |
| 235 |
enum pci_flags_bit { |
| 236 |
PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, |
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PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3, |
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}; |
| 239 |
struct pci_id_info { |
| 240 |
const char *name; |
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u16 vendor_id, device_id, device_id_mask, flags; |
| 242 |
int drv_flags, io_size; |
| 243 |
struct device *(*probe1)(int pci_bus, int pci_devfn, struct device *dev, |
| 244 |
long ioaddr, int irq, int chip_idx, int fnd_cnt); |
| 245 |
}; |
| 246 |
|
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enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, |
| 248 |
HAS_PWR_CTRL=0x10, HAS_MII=0x20, HAS_NWAY=0x40, HAS_CB_FNS=0x80, }; |
| 249 |
static struct device *vortex_probe1(int pci_bus, int pci_devfn, |
| 250 |
struct device *dev, long ioaddr, |
| 251 |
int irq, int dev_id, int card_idx); |
| 252 |
static struct pci_id_info pci_tbl[] = { |
| 253 |
{"3c590 Vortex 10Mbps", 0x10B7, 0x5900, 0xffff, |
| 254 |
PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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{"3c595 Vortex 100baseTx", 0x10B7, 0x5950, 0xffff, |
| 256 |
PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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{"3c595 Vortex 100baseT4", 0x10B7, 0x5951, 0xffff, |
| 258 |
PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
| 259 |
{"3c595 Vortex 100base-MII", 0x10B7, 0x5952, 0xffff, |
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PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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{"3Com Vortex", 0x10B7, 0x5900, 0xff00, |
| 262 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
| 263 |
{"3c900 Boomerang 10baseT", 0x10B7, 0x9000, 0xffff, |
| 264 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
| 265 |
{"3c900 Boomerang 10Mbps Combo", 0x10B7, 0x9001, 0xffff, |
| 266 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
| 267 |
{"3c900 Cyclone 10Mbps Combo", 0x10B7, 0x9005, 0xffff, |
| 268 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 269 |
{"3c900B-FL Cyclone 10base-FL", 0x10B7, 0x900A, 0xffff, |
| 270 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 271 |
{"3c905 Boomerang 100baseTx", 0x10B7, 0x9050, 0xffff, |
| 272 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
| 273 |
{"3c905 Boomerang 100baseT4", 0x10B7, 0x9051, 0xffff, |
| 274 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
| 275 |
{"3c905B Cyclone 100baseTx", 0x10B7, 0x9055, 0xffff, |
| 276 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
| 277 |
{"3c905B Cyclone 10/100/BNC", 0x10B7, 0x9058, 0xffff, |
| 278 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
| 279 |
{"3c905B-FX Cyclone 100baseFx", 0x10B7, 0x905A, 0xffff, |
| 280 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 281 |
{"3c905C Tornado", 0x10B7, 0x9200, 0xffff, |
| 282 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 283 |
{"3c980 Cyclone", 0x10B7, 0x9800, 0xfff0, |
| 284 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 285 |
{"3cSOHO100-TX Hurricane", 0x10B7, 0x7646, 0xffff, |
| 286 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 287 |
{"3c555 Laptop Hurricane", 0x10B7, 0x5055, 0xffff, |
| 288 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
| 289 |
{"3c575 Boomerang CardBus", 0x10B7, 0x5057, 0xffff, |
| 290 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
| 291 |
{"3CCFE575 Cyclone CardBus", 0x10B7, 0x5157, 0xffff, |
| 292 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
| 293 |
128, vortex_probe1}, |
| 294 |
{"3CCFE656 Cyclone CardBus", 0x10B7, 0x6560, 0xffff, |
| 295 |
PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
| 296 |
128, vortex_probe1}, |
| 297 |
{"3c575 series CardBus (unknown version)", 0x10B7, 0x5057, 0xf0ff, |
| 298 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
| 299 |
{"3Com Boomerang (unknown version)", 0x10B7, 0x9000, 0xff00, |
| 300 |
PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
| 301 |
{0,}, /* 0 terminated list. */ |
| 302 |
}; |
| 303 |
|
| 304 |
/* Operational definitions. |
| 305 |
These are not used by other compilation units and thus are not |
| 306 |
exported in a ".h" file. |
| 307 |
|
| 308 |
First the windows. There are eight register windows, with the command |
| 309 |
and status registers available in each. |
| 310 |
*/ |
| 311 |
#define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) |
| 312 |
#define EL3_CMD 0x0e |
| 313 |
#define EL3_STATUS 0x0e |
| 314 |
|
| 315 |
/* The top five bits written to EL3_CMD are a command, the lower |
| 316 |
11 bits are the parameter, if applicable. |
| 317 |
Note that 11 parameters bits was fine for ethernet, but the new chip |
| 318 |
can handle FDDI length frames (~4500 octets) and now parameters count |
| 319 |
32-bit 'Dwords' rather than octets. */ |
| 320 |
|
| 321 |
enum vortex_cmd { |
| 322 |
TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, |
| 323 |
RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, |
| 324 |
UpStall = 6<<11, UpUnstall = (6<<11)+1, |
| 325 |
DownStall = (6<<11)+2, DownUnstall = (6<<11)+3, |
| 326 |
RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, |
| 327 |
FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, |
| 328 |
SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, |
| 329 |
SetTxThreshold = 18<<11, SetTxStart = 19<<11, |
| 330 |
StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11, |
| 331 |
StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,}; |
| 332 |
|
| 333 |
/* The SetRxFilter command accepts the following classes: */ |
| 334 |
enum RxFilter { |
| 335 |
RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 }; |
| 336 |
|
| 337 |
/* Bits in the general status register. */ |
| 338 |
enum vortex_status { |
| 339 |
IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004, |
| 340 |
TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, |
| 341 |
IntReq = 0x0040, StatsFull = 0x0080, |
| 342 |
DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10, |
| 343 |
DMAInProgress = 1<<11, /* DMA controller is still busy.*/ |
| 344 |
CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/ |
| 345 |
}; |
| 346 |
|
| 347 |
/* Register window 1 offsets, the window used in normal operation. |
| 348 |
On the Vortex this window is always mapped at offsets 0x10-0x1f. */ |
| 349 |
enum Window1 { |
| 350 |
TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, |
| 351 |
RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B, |
| 352 |
TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */ |
| 353 |
}; |
| 354 |
enum Window0 { |
| 355 |
Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */ |
| 356 |
Wn0EepromData = 12, /* Window 0: EEPROM results register. */ |
| 357 |
IntrStatus=0x0E, /* Valid in all windows. */ |
| 358 |
}; |
| 359 |
enum Win0_EEPROM_bits { |
| 360 |
EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, |
| 361 |
EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */ |
| 362 |
EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */ |
| 363 |
}; |
| 364 |
/* EEPROM locations. */ |
| 365 |
enum eeprom_offset { |
| 366 |
PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3, |
| 367 |
EtherLink3ID=7, IFXcvrIO=8, IRQLine=9, |
| 368 |
NodeAddr01=10, NodeAddr23=11, NodeAddr45=12, |
| 369 |
DriverTune=13, Checksum=15}; |
| 370 |
|
| 371 |
enum Window2 { /* Window 2. */ |
| 372 |
Wn2_ResetOptions=12, |
| 373 |
}; |
| 374 |
enum Window3 { /* Window 3: MAC/config bits. */ |
| 375 |
Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8, |
| 376 |
}; |
| 377 |
union wn3_config { |
| 378 |
int i; |
| 379 |
struct w3_config_fields { |
| 380 |
unsigned int ram_size:3, ram_width:1, ram_speed:2, rom_size:2; |
| 381 |
int pad8:8; |
| 382 |
unsigned int ram_split:2, pad18:2, xcvr:4, autoselect:1; |
| 383 |
int pad24:7; |
| 384 |
} u; |
| 385 |
}; |
| 386 |
|
| 387 |
enum Window4 { /* Window 4: Xcvr/media bits. */ |
| 388 |
Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10, |
| 389 |
}; |
| 390 |
enum Win4_Media_bits { |
| 391 |
Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */ |
| 392 |
Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */ |
| 393 |
Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */ |
| 394 |
Media_LnkBeat = 0x0800, |
| 395 |
}; |
| 396 |
enum Window7 { /* Window 7: Bus Master control. */ |
| 397 |
Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12, |
| 398 |
}; |
| 399 |
/* Boomerang bus master control registers. */ |
| 400 |
enum MasterCtrl { |
| 401 |
PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c, |
| 402 |
TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38, |
| 403 |
}; |
| 404 |
|
| 405 |
/* The Rx and Tx descriptor lists. |
| 406 |
Caution Alpha hackers: these types are 32 bits! Note also the 8 byte |
| 407 |
alignment contraint on tx_ring[] and rx_ring[]. */ |
| 408 |
#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ |
| 409 |
struct boom_rx_desc { |
| 410 |
u32 next; /* Last entry points to 0. */ |
| 411 |
s32 status; |
| 412 |
u32 addr; /* Up to 63 addr/len pairs possible. */ |
| 413 |
s32 length; /* Set LAST_FRAG to indicate last pair. */ |
| 414 |
}; |
| 415 |
/* Values for the Rx status entry. */ |
| 416 |
enum rx_desc_status { |
| 417 |
RxDComplete=0x00008000, RxDError=0x4000, |
| 418 |
/* See boomerang_rx() for actual error bits */ |
| 419 |
IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27, |
| 420 |
IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31, |
| 421 |
}; |
| 422 |
|
| 423 |
struct boom_tx_desc { |
| 424 |
u32 next; /* Last entry points to 0. */ |
| 425 |
s32 status; /* bits 0:12 length, others see below. */ |
| 426 |
u32 addr; |
| 427 |
s32 length; |
| 428 |
}; |
| 429 |
|
| 430 |
/* Values for the Tx status entry. */ |
| 431 |
enum tx_desc_status { |
| 432 |
CRCDisable=0x2000, TxDComplete=0x8000, |
| 433 |
AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000, |
| 434 |
TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */ |
| 435 |
}; |
| 436 |
|
| 437 |
/* Chip features we care about in vp->capabilities, read from the EEPROM. */ |
| 438 |
enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 }; |
| 439 |
|
| 440 |
struct vortex_private { |
| 441 |
/* The Rx and Tx rings should be quad-word-aligned. */ |
| 442 |
struct boom_rx_desc rx_ring[RX_RING_SIZE]; |
| 443 |
struct boom_tx_desc tx_ring[TX_RING_SIZE]; |
| 444 |
/* The addresses of transmit- and receive-in-place skbuffs. */ |
| 445 |
struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
| 446 |
struct sk_buff* tx_skbuff[TX_RING_SIZE]; |
| 447 |
struct device *next_module; |
| 448 |
void *priv_addr; |
| 449 |
unsigned int cur_rx, cur_tx; /* The next free ring entry */ |
| 450 |
unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ |
| 451 |
struct net_device_stats stats; |
| 452 |
struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */ |
| 453 |
|
| 454 |
/* PCI configuration space information. */ |
| 455 |
u8 pci_bus, pci_devfn; /* PCI bus location, for power management. */ |
| 456 |
char *cb_fn_base; /* CardBus function status addr space. */ |
| 457 |
int chip_id; |
| 458 |
|
| 459 |
/* The remainder are related to chip state, mostly media selection. */ |
| 460 |
unsigned long in_interrupt; |
| 461 |
struct timer_list timer; /* Media selection timer. */ |
| 462 |
int options; /* User-settable misc. driver options. */ |
| 463 |
unsigned int media_override:4, /* Passed-in media type. */ |
| 464 |
default_media:4, /* Read from the EEPROM/Wn3_Config. */ |
| 465 |
full_duplex:1, force_fd:1, autoselect:1, |
| 466 |
bus_master:1, /* Vortex can only do a fragment bus-m. */ |
| 467 |
full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */ |
| 468 |
hw_csums:1, /* Has hardware checksums. */ |
| 469 |
tx_full:1; |
| 470 |
u16 status_enable; |
| 471 |
u16 intr_enable; |
| 472 |
u16 available_media; /* From Wn3_Options. */ |
| 473 |
u16 capabilities, info1, info2; /* Various, from EEPROM. */ |
| 474 |
u16 advertising; /* NWay media advertisement */ |
| 475 |
unsigned char phys[2]; /* MII device addresses. */ |
| 476 |
}; |
| 477 |
|
| 478 |
/* The action to take with a media selection timer tick. |
| 479 |
Note that we deviate from the 3Com order by checking 10base2 before AUI. |
| 480 |
*/ |
| 481 |
enum xcvr_types { |
| 482 |
XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, |
| 483 |
XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10, |
| 484 |
}; |
| 485 |
|
| 486 |
static struct media_table { |
| 487 |
char *name; |
| 488 |
unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */ |
| 489 |
mask:8, /* The transceiver-present bit in Wn3_Config.*/ |
| 490 |
next:8; /* The media type to try next. */ |
| 491 |
int wait; /* Time before we check media status. */ |
| 492 |
} media_tbl[] = { |
| 493 |
{ "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10}, |
| 494 |
{ "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10}, |
| 495 |
{ "undefined", 0, 0x80, XCVR_10baseT, 10000}, |
| 496 |
{ "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10}, |
| 497 |
{ "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10}, |
| 498 |
{ "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10}, |
| 499 |
{ "MII", 0, 0x41, XCVR_10baseT, 3*HZ }, |
| 500 |
{ "undefined", 0, 0x01, XCVR_10baseT, 10000}, |
| 501 |
{ "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ}, |
| 502 |
{ "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ }, |
| 503 |
{ "Default", 0, 0xFF, XCVR_10baseT, 10000}, |
| 504 |
}; |
| 505 |
|
| 506 |
#ifndef CARDBUS |
| 507 |
static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]); |
| 508 |
#endif |
| 509 |
static int vortex_open(struct device *dev); |
| 510 |
static void mdio_sync(long ioaddr, int bits); |
| 511 |
static int mdio_read(long ioaddr, int phy_id, int location); |
| 512 |
static void mdio_write(long ioaddr, int phy_id, int location, int value); |
| 513 |
static void vortex_timer(unsigned long arg); |
| 514 |
static int vortex_start_xmit(struct sk_buff *skb, struct device *dev); |
| 515 |
static int boomerang_start_xmit(struct sk_buff *skb, struct device *dev); |
| 516 |
static int vortex_rx(struct device *dev); |
| 517 |
static int boomerang_rx(struct device *dev); |
| 518 |
static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs); |
| 519 |
static int vortex_close(struct device *dev); |
| 520 |
static void update_stats(long ioaddr, struct device *dev); |
| 521 |
static struct net_device_stats *vortex_get_stats(struct device *dev); |
| 522 |
static void set_rx_mode(struct device *dev); |
| 523 |
static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd); |
| 524 |
static void acpi_wake(int pci_bus, int pci_devfn); |
| 525 |
static void acpi_set_WOL(struct device *dev); |
| 526 |
|
| 527 |
|
| 528 |
/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ |
| 529 |
/* Option count limit only -- unlimited interfaces are supported. */ |
| 530 |
#define MAX_UNITS 8 |
| 531 |
static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,}; |
| 532 |
static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; |
| 533 |
/* A list of all installed Vortex devices, for removing the driver module. */ |
| 534 |
static struct device *root_vortex_dev = NULL; |
| 535 |
|
| 536 |
#ifdef MODULE |
| 537 |
#ifndef CARDBUS |
| 538 |
/* Variables to work-around the Compaq PCI BIOS32 problem. */ |
| 539 |
static int compaq_ioaddr = 0, compaq_irq = 0, compaq_device_id = 0x5900; |
| 540 |
#endif |
| 541 |
|
| 542 |
#ifdef CARDBUS |
| 543 |
|
| 544 |
#include <pcmcia/driver_ops.h> |
| 545 |
|
| 546 |
static dev_node_t *vortex_attach(dev_locator_t *loc) |
| 547 |
{ |
| 548 |
u16 dev_id, vendor_id; |
| 549 |
u32 io; |
| 550 |
u8 bus, devfn, irq; |
| 551 |
struct device *dev; |
| 552 |
int chip_idx; |
| 553 |
|
| 554 |
if (loc->bus != LOC_PCI) return NULL; |
| 555 |
bus = loc->b.pci.bus; devfn = loc->b.pci.devfn; |
| 556 |
pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io); |
| 557 |
pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq); |
| 558 |
pcibios_read_config_word(bus, devfn, PCI_VENDOR_ID, &vendor_id); |
| 559 |
pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id); |
| 560 |
printk(KERN_INFO "vortex_attach(bus %d, function %d, device %4.4x)\n", |
| 561 |
bus, devfn, dev_id); |
| 562 |
io &= ~3; |
| 563 |
if (io == 0 || irq == 0) { |
| 564 |
printk(KERN_ERR "The 3Com CardBus Ethernet interface was not " |
| 565 |
"assigned an %s.\n" KERN_ERR " It will not be activated.\n", |
| 566 |
io == 0 ? "I/O address" : "IRQ"); |
| 567 |
return NULL; |
| 568 |
} |
| 569 |
for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) |
| 570 |
if (vendor_id == pci_tbl[chip_idx].vendor_id |
| 571 |
&& (dev_id & pci_tbl[chip_idx].device_id_mask) == |
| 572 |
pci_tbl[chip_idx].device_id) |
| 573 |
break; |
| 574 |
if (pci_tbl[chip_idx].vendor_id == 0) { /* Compiled out! */ |
| 575 |
printk(KERN_INFO "Unable to match chip type %4.4x %4.4x in " |
| 576 |
"vortex_attach().\n", vendor_id, dev_id); |
| 577 |
return NULL; |
| 578 |
} |
| 579 |
dev = vortex_probe1(bus, devfn, NULL, io, irq, chip_idx, MAX_UNITS+1); |
| 580 |
if (dev) { |
| 581 |
dev_node_t *node = kmalloc(sizeof(dev_node_t), GFP_KERNEL); |
| 582 |
strcpy(node->dev_name, dev->name); |
| 583 |
node->major = node->minor = 0; |
| 584 |
node->next = NULL; |
| 585 |
MOD_INC_USE_COUNT; |
| 586 |
return node; |
| 587 |
} |
| 588 |
return NULL; |
| 589 |
} |
| 590 |
|
| 591 |
static void vortex_detach(dev_node_t *node) |
| 592 |
{ |
| 593 |
struct device **devp, **next; |
| 594 |
printk(KERN_INFO "vortex_detach(%s)\n", node->dev_name); |
| 595 |
for (devp = &root_vortex_dev; *devp; devp = next) { |
| 596 |
next = &((struct vortex_private *)(*devp)->priv)->next_module; |
| 597 |
if (strcmp((*devp)->name, node->dev_name) == 0) break; |
| 598 |
} |
| 599 |
if (*devp) { |
| 600 |
struct device *dev = *devp; |
| 601 |
struct vortex_private *vp = dev->priv; |
| 602 |
if (dev->flags & IFF_UP) |
| 603 |
vortex_close(dev); |
| 604 |
dev->flags &= ~(IFF_UP|IFF_RUNNING); |
| 605 |
unregister_netdev(dev); |
| 606 |
if (vp->cb_fn_base) iounmap(vp->cb_fn_base); |
| 607 |
kfree(dev); |
| 608 |
*devp = *next; |
| 609 |
kfree(vp->priv_addr); |
| 610 |
kfree(node); |
| 611 |
MOD_DEC_USE_COUNT; |
| 612 |
} |
| 613 |
} |
| 614 |
|
| 615 |
struct driver_operations vortex_ops = { |
| 616 |
"3c575_cb", vortex_attach, NULL, NULL, vortex_detach |
| 617 |
}; |
| 618 |
|
| 619 |
#endif /* Cardbus support */ |
| 620 |
|
| 621 |
|
| 622 |
int init_module(void) |
| 623 |
{ |
| 624 |
if (vortex_debug) |
| 625 |
printk(KERN_INFO "%s", version); |
| 626 |
#ifdef CARDBUS |
| 627 |
register_driver(&vortex_ops); |
| 628 |
return 0; |
| 629 |
#else |
| 630 |
return vortex_scan(0, pci_tbl); |
| 631 |
#endif |
| 632 |
} |
| 633 |
|
| 634 |
#else |
| 635 |
int tc59x_probe(struct device *dev) |
| 636 |
{ |
| 637 |
static int did_version = -1; |
| 638 |
if (++did_version <= 0) |
| 639 |
printk(KERN_INFO "%s", version); |
| 640 |
return vortex_scan(dev, pci_tbl); |
| 641 |
} |
| 642 |
#endif /* not MODULE */ |
| 643 |
|
| 644 |
#ifndef CARDBUS |
| 645 |
static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]) |
| 646 |
{ |
| 647 |
int cards_found = 0; |
| 648 |
|
| 649 |
/* Allow an EISA-only driver. */ |
| 650 |
#if defined(CONFIG_PCI) || (defined(MODULE) && !defined(NO_PCI)) |
| 651 |
/* Ideally we would detect all cards in slot order. That would |
| 652 |
be best done a central PCI probe dispatch, which wouldn't work |
| 653 |
well with the current structure. So instead we detect 3Com cards |
| 654 |
in slot order. */ |
| 655 |
if (pcibios_present()) { |
| 656 |
static int pci_index = 0; |
| 657 |
unsigned char pci_bus, pci_device_fn; |
| 658 |
|
| 659 |
for (;pci_index < 0xff; pci_index++) { |
| 660 |
u16 vendor, device, pci_command, new_command; |
| 661 |
int chip_idx, irq; |
| 662 |
long ioaddr; |
| 663 |
|
| 664 |
if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index, |
| 665 |
&pci_bus, &pci_device_fn) |
| 666 |
!= PCIBIOS_SUCCESSFUL) |
| 667 |
break; |
| 668 |
pcibios_read_config_word(pci_bus, pci_device_fn, |
| 669 |
PCI_VENDOR_ID, &vendor); |
| 670 |
pcibios_read_config_word(pci_bus, pci_device_fn, |
| 671 |
PCI_DEVICE_ID, &device); |
| 672 |
for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) |
| 673 |
if (vendor == pci_tbl[chip_idx].vendor_id |
| 674 |
&& (device & pci_tbl[chip_idx].device_id_mask) == |
| 675 |
pci_tbl[chip_idx].device_id) |
| 676 |
break; |
| 677 |
if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */ |
| 678 |
continue; |
| 679 |
|
| 680 |
/* The Cyclone requires config space re-write if powered down. */ |
| 681 |
acpi_wake(pci_bus, pci_device_fn); |
| 682 |
|
| 683 |
{ |
| 684 |
#if LINUX_VERSION_CODE >= 0x20155 |
| 685 |
struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn); |
| 686 |
ioaddr = pdev->base_address[0] & ~3; |
| 687 |
irq = pdev->irq; |
| 688 |
#else |
| 689 |
u32 pci_ioaddr; |
| 690 |
u8 pci_irq_line; |
| 691 |
pcibios_read_config_byte(pci_bus, pci_device_fn, |
| 692 |
PCI_INTERRUPT_LINE, &pci_irq_line); |
| 693 |
pcibios_read_config_dword(pci_bus, pci_device_fn, |
| 694 |
PCI_BASE_ADDRESS_0, &pci_ioaddr); |
| 695 |
ioaddr = pci_ioaddr & ~3;; |
| 696 |
irq = pci_irq_line; |
| 697 |
#endif |
| 698 |
} |
| 699 |
|
| 700 |
if (ioaddr == 0) { |
| 701 |
printk(KERN_WARNING " A 3Com network adapter has been found, " |
| 702 |
"however it has not been assigned an I/O address.\n" |
| 703 |
" You may need to power-cycle the machine for this " |
| 704 |
"device to work!\n"); |
| 705 |
continue; |
| 706 |
} |
| 707 |
|
| 708 |
if (check_region(ioaddr, pci_tbl[chip_idx].io_size)) |
| 709 |
continue; |
| 710 |
|
| 711 |
/* Activate the card. */ |
| 712 |
pcibios_read_config_word(pci_bus, pci_device_fn, |
| 713 |
PCI_COMMAND, &pci_command); |
| 714 |
new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO; |
| 715 |
if (pci_command != new_command) { |
| 716 |
printk(KERN_INFO " The PCI BIOS has not enabled the device " |
| 717 |
"at %d/%d. Updating PCI command %4.4x->%4.4x.\n", |
| 718 |
pci_bus, pci_device_fn, pci_command, new_command); |
| 719 |
pcibios_write_config_word(pci_bus, pci_device_fn, |
| 720 |
PCI_COMMAND, new_command); |
| 721 |
} |
| 722 |
|
| 723 |
dev = vortex_probe1(pci_bus, pci_device_fn, dev, ioaddr, irq, |
| 724 |
chip_idx, cards_found); |
| 725 |
|
| 726 |
if (dev) { |
| 727 |
/* Get and check the latency values. On the 3c590 series |
| 728 |
the latency timer must be set to the maximum value to avoid |
| 729 |
data corruption that occurs when the timer expires during |
| 730 |
a transfer -- a bug in the Vortex chip only. */ |
| 731 |
u8 pci_latency; |
| 732 |
u8 new_latency = (device & 0xff00) == 0x5900 ? 248 : 32; |
| 733 |
|
| 734 |
pcibios_read_config_byte(pci_bus, pci_device_fn, |
| 735 |
PCI_LATENCY_TIMER, &pci_latency); |
| 736 |
if (pci_latency < new_latency) { |
| 737 |
printk(KERN_INFO "%s: Overriding PCI latency" |
| 738 |
" timer (CFLT) setting of %d, new value is %d.\n", |
| 739 |
dev->name, pci_latency, new_latency); |
| 740 |
pcibios_write_config_byte(pci_bus, pci_device_fn, |
| 741 |
PCI_LATENCY_TIMER, new_latency); |
| 742 |
} |
| 743 |
dev = 0; |
| 744 |
cards_found++; |
| 745 |
} |
| 746 |
} |
| 747 |
} |
| 748 |
#endif /* NO_PCI */ |
| 749 |
|
| 750 |
/* Now check all slots of the EISA bus. */ |
| 751 |
if (EISA_bus) { |
| 752 |
static long ioaddr = 0x1000; |
| 753 |
for ( ; ioaddr < 0x9000; ioaddr += 0x1000) { |
| 754 |
int device_id; |
| 755 |
if (check_region(ioaddr, VORTEX_TOTAL_SIZE)) |
| 756 |
continue; |
| 757 |
/* Check the standard EISA ID register for an encoded '3Com'. */ |
| 758 |
if (inw(ioaddr + 0xC80) != 0x6d50) |
| 759 |
continue; |
| 760 |
/* Check for a product that we support, 3c59{2,7} any rev. */ |
| 761 |
device_id = (inb(ioaddr + 0xC82)<<8) + inb(ioaddr + 0xC83); |
| 762 |
if ((device_id & 0xFF00) != 0x5900) |
| 763 |
continue; |
| 764 |
vortex_probe1(0, 0, dev, ioaddr, inw(ioaddr + 0xC88) >> 12, |
| 765 |
4, cards_found); |
| 766 |
dev = 0; |
| 767 |
cards_found++; |
| 768 |
} |
| 769 |
} |
| 770 |
|
| 771 |
#ifdef MODULE |
| 772 |
/* Special code to work-around the Compaq PCI BIOS32 problem. */ |
| 773 |
if (compaq_ioaddr) { |
| 774 |
vortex_probe1(0, 0, dev, compaq_ioaddr, compaq_irq, |
| 775 |
compaq_device_id, cards_found++); |
| 776 |
dev = 0; |
| 777 |
} |
| 778 |
#endif |
| 779 |
|
| 780 |
return cards_found ? 0 : -ENODEV; |
| 781 |
} |
| 782 |
#endif /* ! Cardbus */ |
| 783 |
|
| 784 |
static struct device *vortex_probe1(int pci_bus, int pci_devfn, |
| 785 |
struct device *dev, long ioaddr, |
| 786 |
int irq, int chip_idx, int card_idx) |
| 787 |
{ |
| 788 |
struct vortex_private *vp; |
| 789 |
int option; |
| 790 |
unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ |
| 791 |
int i; |
| 792 |
|
| 793 |
dev = init_etherdev(dev, 0); |
| 794 |
|
| 795 |
printk(KERN_INFO "%s: 3Com %s at 0x%lx, ", |
| 796 |
dev->name, pci_tbl[chip_idx].name, ioaddr); |
| 797 |
|
| 798 |
dev->base_addr = ioaddr; |
| 799 |
dev->irq = irq; |
| 800 |
dev->mtu = mtu; |
| 801 |
|
| 802 |
/* Make certain the descriptor lists are aligned. */ |
| 803 |
{ |
| 804 |
void *mem = kmalloc(sizeof(*vp) + 15, GFP_KERNEL); |
| 805 |
vp = (void *)(((long)mem + 15) & ~15); |
| 806 |
vp->priv_addr = mem; |
| 807 |
} |
| 808 |
memset(vp, 0, sizeof(*vp)); |
| 809 |
dev->priv = vp; |
| 810 |
|
| 811 |
vp->next_module = root_vortex_dev; |
| 812 |
root_vortex_dev = dev; |
| 813 |
|
| 814 |
vp->chip_id = chip_idx; |
| 815 |
vp->pci_bus = pci_bus; |
| 816 |
vp->pci_devfn = pci_devfn; |
| 817 |
|
| 818 |
/* The lower four bits are the media type. */ |
| 819 |
if (dev->mem_start) |
| 820 |
option = dev->mem_start; |
| 821 |
else if (card_idx < MAX_UNITS) |
| 822 |
option = options[card_idx]; |
| 823 |
else |
| 824 |
option = -1; |
| 825 |
|
| 826 |
if (option >= 0) { |
| 827 |
vp->media_override = ((option & 7) == 2) ? 0 : option & 15; |
| 828 |
vp->full_duplex = (option & 0x200) ? 1 : 0; |
| 829 |
vp->bus_master = (option & 16) ? 1 : 0; |
| 830 |
} else { |
| 831 |
vp->media_override = 7; |
| 832 |
vp->full_duplex = 0; |
| 833 |
vp->bus_master = 0; |
| 834 |
} |
| 835 |
if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) |
| 836 |
vp->full_duplex = 1; |
| 837 |
|
| 838 |
vp->force_fd = vp->full_duplex; |
| 839 |
vp->options = option; |
| 840 |
|
| 841 |
/* Read the station address from the EEPROM. */ |
| 842 |
EL3WINDOW(0); |
| 843 |
for (i = 0; i < 0x40; i++) { |
| 844 |
int timer; |
| 845 |
#ifdef CARDBUS |
| 846 |
outw(0x230 + i, ioaddr + Wn0EepromCmd); |
| 847 |
#else |
| 848 |
outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd); |
| 849 |
#endif |
| 850 |
/* Pause for at least 162 us. for the read to take place. */ |
| 851 |
for (timer = 10; timer >= 0; timer--) { |
| 852 |
udelay(162); |
| 853 |
if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0) |
| 854 |
break; |
| 855 |
} |
| 856 |
eeprom[i] = inw(ioaddr + Wn0EepromData); |
| 857 |
} |
| 858 |
for (i = 0; i < 0x18; i++) |
| 859 |
checksum ^= eeprom[i]; |
| 860 |
checksum = (checksum ^ (checksum >> 8)) & 0xff; |
| 861 |
if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */ |
| 862 |
while (i < 0x21) |
| 863 |
checksum ^= eeprom[i++]; |
| 864 |
checksum = (checksum ^ (checksum >> 8)) & 0xff; |
| 865 |
} |
| 866 |
if (checksum != 0x00) |
| 867 |
printk(" ***INVALID CHECKSUM %4.4x*** ", checksum); |
| 868 |
|
| 869 |
for (i = 0; i < 3; i++) |
| 870 |
((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]); |
| 871 |
for (i = 0; i < 6; i++) |
| 872 |
printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]); |
| 873 |
EL3WINDOW(2); |
| 874 |
for (i = 0; i < 6; i++) |
| 875 |
outb(dev->dev_addr[i], ioaddr + i); |
| 876 |
|
| 877 |
#ifdef __sparc__ |
| 878 |
printk(", IRQ %s\n", __irq_itoa(dev->irq)); |
| 879 |
#else |
| 880 |
printk(", IRQ %d\n", dev->irq); |
| 881 |
/* Tell them about an invalid IRQ. */ |
| 882 |
if (vortex_debug && (dev->irq <= 0 || dev->irq >= NR_IRQS)) |
| 883 |
printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n", |
| 884 |
dev->irq); |
| 885 |
#endif |
| 886 |
|
| 887 |
if (pci_tbl[vp->chip_id].drv_flags & HAS_CB_FNS) { |
| 888 |
u32 fn_st_addr; /* Cardbus function status space */ |
| 889 |
pcibios_read_config_dword(pci_bus, pci_devfn, PCI_BASE_ADDRESS_2, |
| 890 |
&fn_st_addr); |
| 891 |
if (fn_st_addr) |
| 892 |
vp->cb_fn_base = ioremap(fn_st_addr & ~3, 128); |
| 893 |
printk("%s: CardBus functions mapped %8.8x->%p (PCMCIA committee" |
| 894 |
" brain-damage).\n", dev->name, fn_st_addr, vp->cb_fn_base); |
| 895 |
EL3WINDOW(2); |
| 896 |
outw(0x10 | inw(ioaddr + Wn2_ResetOptions), ioaddr + Wn2_ResetOptions); |
| 897 |
} |
| 898 |
|
| 899 |
/* Extract our information from the EEPROM data. */ |
| 900 |
vp->info1 = eeprom[13]; |
| 901 |
vp->info2 = eeprom[15]; |
| 902 |
vp->capabilities = eeprom[16]; |
| 903 |
|
| 904 |
if (vp->info1 & 0x8000) |
| 905 |
vp->full_duplex = 1; |
| 906 |
|
| 907 |
{ |
| 908 |
char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"}; |
| 909 |
union wn3_config config; |
| 910 |
EL3WINDOW(3); |
| 911 |
vp->available_media = inw(ioaddr + Wn3_Options); |
| 912 |
if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ |
| 913 |
vp->available_media = 0x40; |
| 914 |
config.i = inl(ioaddr + Wn3_Config); |
| 915 |
if (vortex_debug > 1) |
| 916 |
printk(KERN_DEBUG " Internal config register is %4.4x, " |
| 917 |
"transceivers %#x.\n", config.i, inw(ioaddr + Wn3_Options)); |
| 918 |
printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", |
| 919 |
8 << config.u.ram_size, |
| 920 |
config.u.ram_width ? "word" : "byte", |
| 921 |
ram_split[config.u.ram_split], |
| 922 |
config.u.autoselect ? "autoselect/" : "", |
| 923 |
config.u.xcvr > XCVR_ExtMII ? "<invalid transceiver>" : |
| 924 |
media_tbl[config.u.xcvr].name); |
| 925 |
vp->default_media = config.u.xcvr; |
| 926 |
vp->autoselect = config.u.autoselect; |
| 927 |
} |
| 928 |
|
| 929 |
if (vp->media_override != 7) { |
| 930 |
printk(KERN_INFO " Media override to transceiver type %d (%s).\n", |
| 931 |
vp->media_override, media_tbl[vp->media_override].name); |
| 932 |
dev->if_port = vp->media_override; |
| 933 |
} else |
| 934 |
dev->if_port = vp->default_media; |
| 935 |
|
| 936 |
if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { |
| 937 |
int phy, phy_idx = 0; |
| 938 |
EL3WINDOW(4); |
| 939 |
mii_preamble_required++; |
| 940 |
mii_preamble_required++; |
| 941 |
mdio_read(ioaddr, 24, 1); |
| 942 |
for (phy = 1; phy <= 32 && phy_idx < sizeof(vp->phys); phy++) { |
| 943 |
int mii_status, phyx = phy & 0x1f; |
| 944 |
mii_status = mdio_read(ioaddr, phyx, 1); |
| 945 |
if (mii_status && mii_status != 0xffff) { |
| 946 |
vp->phys[phy_idx++] = phyx; |
| 947 |
printk(KERN_INFO " MII transceiver found at address %d," |
| 948 |
" status %4x.\n", phyx, mii_status); |
| 949 |
if ((mii_status & 0x0040) == 0) |
| 950 |
mii_preamble_required++; |
| 951 |
} |
| 952 |
} |
| 953 |
mii_preamble_required--; |
| 954 |
if (phy_idx == 0) { |
| 955 |
printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n"); |
| 956 |
vp->phys[0] = 24; |
| 957 |
} else { |
| 958 |
vp->advertising = mdio_read(ioaddr, vp->phys[0], 4); |
| 959 |
if (vp->full_duplex) { |
| 960 |
/* Only advertise the FD media types. */ |
| 961 |
vp->advertising &= ~0x02A0; |
| 962 |
mdio_write(ioaddr, vp->phys[0], 4, vp->advertising); |
| 963 |
} |
| 964 |
} |
| 965 |
} |
| 966 |
|
| 967 |
if (vp->capabilities & CapPwrMgmt) |
| 968 |
acpi_set_WOL(dev); |
| 969 |
|
| 970 |
if (vp->capabilities & CapBusMaster) { |
| 971 |
vp->full_bus_master_tx = 1; |
| 972 |
printk(KERN_INFO" Enabling bus-master transmits and %s receives.\n", |
| 973 |
(vp->info2 & 1) ? "early" : "whole-frame" ); |
| 974 |
vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2; |
| 975 |
} |
| 976 |
|
| 977 |
/* We do a request_region() to register /proc/ioports info. */ |
| 978 |
request_region(ioaddr, pci_tbl[chip_idx].io_size, dev->name); |
| 979 |
|
| 980 |
/* The 3c59x-specific entries in the device structure. */ |
| 981 |
dev->open = &vortex_open; |
| 982 |
dev->hard_start_xmit = &vortex_start_xmit; |
| 983 |
dev->stop = &vortex_close; |
| 984 |
dev->get_stats = &vortex_get_stats; |
| 985 |
dev->do_ioctl = &vortex_ioctl; |
| 986 |
dev->set_multicast_list = &set_rx_mode; |
| 987 |
|
| 988 |
return dev; |
| 989 |
} |
| 990 |
|
| 991 |
|
| 992 |
static int |
| 993 |
vortex_open(struct device *dev) |
| 994 |
{ |
| 995 |
long ioaddr = dev->base_addr; |
| 996 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 997 |
union wn3_config config; |
| 998 |
int i; |
| 999 |
|
| 1000 |
/* Should be if(HAS_ACPI) */ |
| 1001 |
acpi_wake(vp->pci_bus, vp->pci_devfn); |
| 1002 |
|
| 1003 |
/* Before initializing select the active media port. */ |
| 1004 |
EL3WINDOW(3); |
| 1005 |
config.i = inl(ioaddr + Wn3_Config); |
| 1006 |
|
| 1007 |
if (vp->media_override != 7) { |
| 1008 |
if (vortex_debug > 1) |
| 1009 |
printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n", |
| 1010 |
dev->name, vp->media_override, |
| 1011 |
media_tbl[vp->media_override].name); |
| 1012 |
dev->if_port = vp->media_override; |
| 1013 |
} else if (vp->autoselect) { |
| 1014 |
if (pci_tbl[vp->chip_id].drv_flags & HAS_NWAY) |
| 1015 |
dev->if_port = XCVR_NWAY; |
| 1016 |
else { |
| 1017 |
/* Find first available media type, starting with 100baseTx. */ |
| 1018 |
dev->if_port = XCVR_100baseTx; |
| 1019 |
while (! (vp->available_media & media_tbl[dev->if_port].mask)) |
| 1020 |
dev->if_port = media_tbl[dev->if_port].next; |
| 1021 |
} |
| 1022 |
} else |
| 1023 |
dev->if_port = vp->default_media; |
| 1024 |
|
| 1025 |
init_timer(&vp->timer); |
| 1026 |
vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait); |
| 1027 |
vp->timer.data = (unsigned long)dev; |
| 1028 |
vp->timer.function = &vortex_timer; /* timer handler */ |
| 1029 |
add_timer(&vp->timer); |
| 1030 |
|
| 1031 |
if (vortex_debug > 1) |
| 1032 |
printk(KERN_DEBUG "%s: Initial media type %s.\n", |
| 1033 |
dev->name, media_tbl[dev->if_port].name); |
| 1034 |
|
| 1035 |
vp->full_duplex = vp->force_fd; |
| 1036 |
config.u.xcvr = dev->if_port; |
| 1037 |
if ( ! (pci_tbl[vp->chip_id].drv_flags & HAS_NWAY)) |
| 1038 |
outl(config.i, ioaddr + Wn3_Config); |
| 1039 |
|
| 1040 |
if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { |
| 1041 |
int mii_reg1, mii_reg5; |
| 1042 |
EL3WINDOW(4); |
| 1043 |
/* Read BMSR (reg1) only to clear old status. */ |
| 1044 |
mii_reg1 = mdio_read(ioaddr, vp->phys[0], 1); |
| 1045 |
mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5); |
| 1046 |
if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) |
| 1047 |
; /* No MII device or no link partner report */ |
| 1048 |
else if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */ |
| 1049 |
|| (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */ |
| 1050 |
vp->full_duplex = 1; |
| 1051 |
if (vortex_debug > 1) |
| 1052 |
printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x," |
| 1053 |
" setting %s-duplex.\n", dev->name, vp->phys[0], |
| 1054 |
mii_reg1, mii_reg5, vp->full_duplex ? "full" : "half"); |
| 1055 |
EL3WINDOW(3); |
| 1056 |
} |
| 1057 |
|
| 1058 |
/* Set the full-duplex bit. */ |
| 1059 |
outb(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | |
| 1060 |
(dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl); |
| 1061 |
|
| 1062 |
if (vortex_debug > 1) { |
| 1063 |
printk(KERN_DEBUG "%s: vortex_open() InternalConfig %8.8x.\n", |
| 1064 |
dev->name, config.i); |
| 1065 |
} |
| 1066 |
|
| 1067 |
outw(TxReset, ioaddr + EL3_CMD); |
| 1068 |
for (i = 2000; i >= 0 ; i--) |
| 1069 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1070 |
break; |
| 1071 |
|
| 1072 |
outw(RxReset, ioaddr + EL3_CMD); |
| 1073 |
/* Wait a few ticks for the RxReset command to complete. */ |
| 1074 |
for (i = 2000; i >= 0 ; i--) |
| 1075 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1076 |
break; |
| 1077 |
|
| 1078 |
outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD); |
| 1079 |
|
| 1080 |
/* Use the now-standard shared IRQ implementation. */ |
| 1081 |
if (request_irq(dev->irq, &vortex_interrupt, SA_SHIRQ, dev->name, dev)) { |
| 1082 |
return -EAGAIN; |
| 1083 |
} |
| 1084 |
|
| 1085 |
if (vortex_debug > 1) { |
| 1086 |
EL3WINDOW(4); |
| 1087 |
printk(KERN_DEBUG "%s: vortex_open() irq %d media status %4.4x.\n", |
| 1088 |
dev->name, dev->irq, inw(ioaddr + Wn4_Media)); |
| 1089 |
} |
| 1090 |
|
| 1091 |
/* Set the station address and mask in window 2 each time opened. */ |
| 1092 |
EL3WINDOW(2); |
| 1093 |
for (i = 0; i < 6; i++) |
| 1094 |
outb(dev->dev_addr[i], ioaddr + i); |
| 1095 |
for (; i < 12; i+=2) |
| 1096 |
outw(0, ioaddr + i); |
| 1097 |
|
| 1098 |
if (dev->if_port == XCVR_10base2) |
| 1099 |
/* Start the thinnet transceiver. We should really wait 50ms...*/ |
| 1100 |
outw(StartCoax, ioaddr + EL3_CMD); |
| 1101 |
if (dev->if_port != XCVR_NWAY) { |
| 1102 |
EL3WINDOW(4); |
| 1103 |
outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) | |
| 1104 |
media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); |
| 1105 |
} |
| 1106 |
|
| 1107 |
/* Switch to the stats window, and clear all stats by reading. */ |
| 1108 |
outw(StatsDisable, ioaddr + EL3_CMD); |
| 1109 |
EL3WINDOW(6); |
| 1110 |
for (i = 0; i < 10; i++) |
| 1111 |
inb(ioaddr + i); |
| 1112 |
inw(ioaddr + 10); |
| 1113 |
inw(ioaddr + 12); |
| 1114 |
/* New: On the Vortex we must also clear the BadSSD counter. */ |
| 1115 |
EL3WINDOW(4); |
| 1116 |
inb(ioaddr + 12); |
| 1117 |
/* ..and on the Boomerang we enable the extra statistics bits. */ |
| 1118 |
outw(0x0040, ioaddr + Wn4_NetDiag); |
| 1119 |
|
| 1120 |
/* Switch to register set 7 for normal use. */ |
| 1121 |
EL3WINDOW(7); |
| 1122 |
|
| 1123 |
if (vp->full_bus_master_rx) { /* Boomerang bus master. */ |
| 1124 |
vp->cur_rx = vp->dirty_rx = 0; |
| 1125 |
/* Initialize the RxEarly register as recommended. */ |
| 1126 |
outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD); |
| 1127 |
outl(0x0020, ioaddr + PktStatus); |
| 1128 |
if (vortex_debug > 2) |
| 1129 |
printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name); |
| 1130 |
for (i = 0; i < RX_RING_SIZE; i++) { |
| 1131 |
struct sk_buff *skb; |
| 1132 |
vp->rx_ring[i].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[i+1])); |
| 1133 |
vp->rx_ring[i].status = 0; /* Clear complete bit. */ |
| 1134 |
vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); |
| 1135 |
skb = dev_alloc_skb(PKT_BUF_SZ); |
| 1136 |
vp->rx_skbuff[i] = skb; |
| 1137 |
if (skb == NULL) |
| 1138 |
break; /* Bad news! */ |
| 1139 |
skb->dev = dev; /* Mark as being used by this device. */ |
| 1140 |
#if LINUX_VERSION_CODE >= 0x10300 |
| 1141 |
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
| 1142 |
vp->rx_ring[i].addr = cpu_to_le32(virt_to_bus(skb->tail)); |
| 1143 |
#else |
| 1144 |
vp->rx_ring[i].addr = virt_to_bus(skb->data); |
| 1145 |
#endif |
| 1146 |
} |
| 1147 |
/* Wrap the ring. */ |
| 1148 |
vp->rx_ring[i-1].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[0])); |
| 1149 |
outl(virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr); |
| 1150 |
} |
| 1151 |
if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */ |
| 1152 |
dev->hard_start_xmit = &boomerang_start_xmit; |
| 1153 |
vp->cur_tx = vp->dirty_tx = 0; |
| 1154 |
outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */ |
| 1155 |
/* Clear the Tx ring. */ |
| 1156 |
for (i = 0; i < TX_RING_SIZE; i++) |
| 1157 |
vp->tx_skbuff[i] = 0; |
| 1158 |
outl(0, ioaddr + DownListPtr); |
| 1159 |
} |
| 1160 |
/* Set reciever mode: presumably accept b-case and phys addr only. */ |
| 1161 |
set_rx_mode(dev); |
| 1162 |
outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */ |
| 1163 |
|
| 1164 |
vp->in_interrupt = 0; |
| 1165 |
dev->tbusy = 0; |
| 1166 |
dev->interrupt = 0; |
| 1167 |
dev->start = 1; |
| 1168 |
|
| 1169 |
outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */ |
| 1170 |
outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */ |
| 1171 |
/* Allow status bits to be seen. */ |
| 1172 |
vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete| |
| 1173 |
(vp->full_bus_master_tx ? DownComplete : TxAvailable) | |
| 1174 |
(vp->full_bus_master_rx ? UpComplete : RxComplete) | |
| 1175 |
(vp->bus_master ? DMADone : 0); |
| 1176 |
vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable | RxComplete | |
| 1177 |
StatsFull | HostError | TxComplete | IntReq |
| 1178 |
| (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete; |
| 1179 |
outw(vp->status_enable, ioaddr + EL3_CMD); |
| 1180 |
/* Ack all pending events, and set active indicator mask. */ |
| 1181 |
outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, |
| 1182 |
ioaddr + EL3_CMD); |
| 1183 |
outw(vp->intr_enable, ioaddr + EL3_CMD); |
| 1184 |
if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
| 1185 |
writel(0x8000, vp->cb_fn_base + 4); |
| 1186 |
|
| 1187 |
MOD_INC_USE_COUNT; |
| 1188 |
|
| 1189 |
return 0; |
| 1190 |
} |
| 1191 |
|
| 1192 |
static void vortex_timer(unsigned long data) |
| 1193 |
{ |
| 1194 |
struct device *dev = (struct device *)data; |
| 1195 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1196 |
long ioaddr = dev->base_addr; |
| 1197 |
int next_tick = 60*HZ; |
| 1198 |
int ok = 0; |
| 1199 |
int media_status, mii_status, old_window; |
| 1200 |
|
| 1201 |
if (vortex_debug > 1) |
| 1202 |
printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n", |
| 1203 |
dev->name, media_tbl[dev->if_port].name); |
| 1204 |
|
| 1205 |
disable_irq(dev->irq); |
| 1206 |
old_window = inw(ioaddr + EL3_CMD) >> 13; |
| 1207 |
EL3WINDOW(4); |
| 1208 |
media_status = inw(ioaddr + Wn4_Media); |
| 1209 |
switch (dev->if_port) { |
| 1210 |
case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx: |
| 1211 |
if (media_status & Media_LnkBeat) { |
| 1212 |
ok = 1; |
| 1213 |
if (vortex_debug > 1) |
| 1214 |
printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n", |
| 1215 |
dev->name, media_tbl[dev->if_port].name, media_status); |
| 1216 |
} else if (vortex_debug > 1) |
| 1217 |
printk(KERN_DEBUG "%s: Media %s is has no link beat, %x.\n", |
| 1218 |
dev->name, media_tbl[dev->if_port].name, media_status); |
| 1219 |
break; |
| 1220 |
case XCVR_MII: case XCVR_NWAY: |
| 1221 |
mii_status = mdio_read(ioaddr, vp->phys[0], 1); |
| 1222 |
ok = 1; |
| 1223 |
if (debug > 1) |
| 1224 |
printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n", |
| 1225 |
dev->name, mii_status); |
| 1226 |
if (mii_status & 0x0004) { |
| 1227 |
int mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5); |
| 1228 |
if (! vp->force_fd && mii_reg5 != 0xffff) { |
| 1229 |
int duplex = (mii_reg5&0x0100) || |
| 1230 |
(mii_reg5 & 0x01C0) == 0x0040; |
| 1231 |
if (vp->full_duplex != duplex) { |
| 1232 |
vp->full_duplex = duplex; |
| 1233 |
printk(KERN_INFO "%s: Setting %s-duplex based on MII " |
| 1234 |
"#%d link partner capability of %4.4x.\n", |
| 1235 |
dev->name, vp->full_duplex ? "full" : "half", |
| 1236 |
vp->phys[0], mii_reg5); |
| 1237 |
/* Set the full-duplex bit. */ |
| 1238 |
outb((vp->full_duplex ? 0x20 : 0) | |
| 1239 |
(dev->mtu > 1500 ? 0x40 : 0), |
| 1240 |
ioaddr + Wn3_MAC_Ctrl); |
| 1241 |
} |
| 1242 |
next_tick = 60*HZ; |
| 1243 |
} |
| 1244 |
} |
| 1245 |
break; |
| 1246 |
default: /* Other media types handled by Tx timeouts. */ |
| 1247 |
if (vortex_debug > 1) |
| 1248 |
printk(KERN_DEBUG "%s: Media %s is has no indication, %x.\n", |
| 1249 |
dev->name, media_tbl[dev->if_port].name, media_status); |
| 1250 |
ok = 1; |
| 1251 |
} |
| 1252 |
if ( ! ok) { |
| 1253 |
union wn3_config config; |
| 1254 |
|
| 1255 |
do { |
| 1256 |
dev->if_port = media_tbl[dev->if_port].next; |
| 1257 |
} while ( ! (vp->available_media & media_tbl[dev->if_port].mask)); |
| 1258 |
if (dev->if_port == XCVR_Default) { /* Go back to default. */ |
| 1259 |
dev->if_port = vp->default_media; |
| 1260 |
if (vortex_debug > 1) |
| 1261 |
printk(KERN_DEBUG "%s: Media selection failing, using default " |
| 1262 |
"%s port.\n", |
| 1263 |
dev->name, media_tbl[dev->if_port].name); |
| 1264 |
} else { |
| 1265 |
if (vortex_debug > 1) |
| 1266 |
printk(KERN_DEBUG "%s: Media selection failed, now trying " |
| 1267 |
"%s port.\n", |
| 1268 |
dev->name, media_tbl[dev->if_port].name); |
| 1269 |
next_tick = media_tbl[dev->if_port].wait; |
| 1270 |
} |
| 1271 |
outw((media_status & ~(Media_10TP|Media_SQE)) | |
| 1272 |
media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); |
| 1273 |
|
| 1274 |
EL3WINDOW(3); |
| 1275 |
config.i = inl(ioaddr + Wn3_Config); |
| 1276 |
config.u.xcvr = dev->if_port; |
| 1277 |
outl(config.i, ioaddr + Wn3_Config); |
| 1278 |
|
| 1279 |
outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax, |
| 1280 |
ioaddr + EL3_CMD); |
| 1281 |
} |
| 1282 |
EL3WINDOW(old_window); |
| 1283 |
enable_irq(dev->irq); |
| 1284 |
|
| 1285 |
if (vortex_debug > 2) |
| 1286 |
printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n", |
| 1287 |
dev->name, media_tbl[dev->if_port].name); |
| 1288 |
|
| 1289 |
vp->timer.expires = RUN_AT(next_tick); |
| 1290 |
add_timer(&vp->timer); |
| 1291 |
return; |
| 1292 |
} |
| 1293 |
|
| 1294 |
static void vortex_tx_timeout(struct device *dev) |
| 1295 |
{ |
| 1296 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1297 |
long ioaddr = dev->base_addr; |
| 1298 |
int j; |
| 1299 |
|
| 1300 |
printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n", |
| 1301 |
dev->name, inb(ioaddr + TxStatus), |
| 1302 |
inw(ioaddr + EL3_STATUS)); |
| 1303 |
/* Slight code bloat to be user friendly. */ |
| 1304 |
if ((inb(ioaddr + TxStatus) & 0x88) == 0x88) |
| 1305 |
printk(KERN_ERR "%s: Transmitter encountered 16 collisions --" |
| 1306 |
" network cable problem?\n", dev->name); |
| 1307 |
if (inw(ioaddr + EL3_STATUS) & IntLatch) { |
| 1308 |
printk(KERN_ERR "%s: Interrupt posted but not delivered --" |
| 1309 |
" IRQ blocked by another device?\n", dev->name); |
| 1310 |
/* Bad idea here.. but we might as well handle a few events. */ |
| 1311 |
vortex_interrupt(dev->irq, dev, 0); |
| 1312 |
} |
| 1313 |
|
| 1314 |
#if ! defined(final_version) && LINUX_VERSION_CODE >= 0x10300 |
| 1315 |
if (vp->full_bus_master_tx) { |
| 1316 |
int i; |
| 1317 |
printk(KERN_DEBUG " Flags; bus-master %d, full %d; dirty %d " |
| 1318 |
"current %d.\n", |
| 1319 |
vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx, vp->cur_tx); |
| 1320 |
printk(KERN_DEBUG " Transmit list %8.8x vs. %p.\n", |
| 1321 |
inl(ioaddr + DownListPtr), |
| 1322 |
&vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]); |
| 1323 |
for (i = 0; i < TX_RING_SIZE; i++) { |
| 1324 |
printk(KERN_DEBUG " %d: @%p length %8.8x status %8.8x\n", i, |
| 1325 |
&vp->tx_ring[i], |
| 1326 |
le32_to_cpu(vp->tx_ring[i].length), |
| 1327 |
le32_to_cpu(vp->tx_ring[i].status)); |
| 1328 |
} |
| 1329 |
} |
| 1330 |
#endif |
| 1331 |
outw(TxReset, ioaddr + EL3_CMD); |
| 1332 |
for (j = 200; j >= 0 ; j--) |
| 1333 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1334 |
break; |
| 1335 |
|
| 1336 |
vp->stats.tx_errors++; |
| 1337 |
if (vp->full_bus_master_tx) { |
| 1338 |
if (vortex_debug > 0) |
| 1339 |
printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", |
| 1340 |
dev->name); |
| 1341 |
if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0) |
| 1342 |
outl(virt_to_bus(&vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]), |
| 1343 |
ioaddr + DownListPtr); |
| 1344 |
if (vp->tx_full && (vp->cur_tx - vp->dirty_tx <= TX_RING_SIZE - 1)) { |
| 1345 |
vp->tx_full = 0; |
| 1346 |
clear_bit(0, (void*)&dev->tbusy); |
| 1347 |
} |
| 1348 |
outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); |
| 1349 |
outw(DownUnstall, ioaddr + EL3_CMD); |
| 1350 |
} else |
| 1351 |
vp->stats.tx_dropped++; |
| 1352 |
|
| 1353 |
/* Issue Tx Enable */ |
| 1354 |
outw(TxEnable, ioaddr + EL3_CMD); |
| 1355 |
dev->trans_start = jiffies; |
| 1356 |
|
| 1357 |
/* Switch to register set 7 for normal use. */ |
| 1358 |
EL3WINDOW(7); |
| 1359 |
} |
| 1360 |
|
| 1361 |
/* |
| 1362 |
* Handle uncommon interrupt sources. This is a separate routine to minimize |
| 1363 |
* the cache impact. |
| 1364 |
*/ |
| 1365 |
static void |
| 1366 |
vortex_error(struct device *dev, int status) |
| 1367 |
{ |
| 1368 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1369 |
long ioaddr = dev->base_addr; |
| 1370 |
int do_tx_reset = 0; |
| 1371 |
int i; |
| 1372 |
|
| 1373 |
if (status & TxComplete) { /* Really "TxError" for us. */ |
| 1374 |
unsigned char tx_status = inb(ioaddr + TxStatus); |
| 1375 |
/* Presumably a tx-timeout. We must merely re-enable. */ |
| 1376 |
if (vortex_debug > 2 |
| 1377 |
|| (tx_status != 0x88 && vortex_debug > 0)) |
| 1378 |
printk(KERN_DEBUG"%s: Transmit error, Tx status register %2.2x.\n", |
| 1379 |
dev->name, tx_status); |
| 1380 |
if (tx_status & 0x14) vp->stats.tx_fifo_errors++; |
| 1381 |
if (tx_status & 0x38) vp->stats.tx_aborted_errors++; |
| 1382 |
outb(0, ioaddr + TxStatus); |
| 1383 |
if (tx_status & 0x30) |
| 1384 |
do_tx_reset = 1; |
| 1385 |
else /* Merely re-enable the transmitter. */ |
| 1386 |
outw(TxEnable, ioaddr + EL3_CMD); |
| 1387 |
} |
| 1388 |
if (status & RxEarly) { /* Rx early is unused. */ |
| 1389 |
vortex_rx(dev); |
| 1390 |
outw(AckIntr | RxEarly, ioaddr + EL3_CMD); |
| 1391 |
} |
| 1392 |
if (status & StatsFull) { /* Empty statistics. */ |
| 1393 |
static int DoneDidThat = 0; |
| 1394 |
if (vortex_debug > 4) |
| 1395 |
printk(KERN_DEBUG "%s: Updating stats.\n", dev->name); |
| 1396 |
update_stats(ioaddr, dev); |
| 1397 |
/* HACK: Disable statistics as an interrupt source. */ |
| 1398 |
/* This occurs when we have the wrong media type! */ |
| 1399 |
if (DoneDidThat == 0 && |
| 1400 |
inw(ioaddr + EL3_STATUS) & StatsFull) { |
| 1401 |
printk(KERN_WARNING "%s: Updating statistics failed, disabling " |
| 1402 |
"stats as an interrupt source.\n", dev->name); |
| 1403 |
EL3WINDOW(5); |
| 1404 |
outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD); |
| 1405 |
EL3WINDOW(7); |
| 1406 |
DoneDidThat++; |
| 1407 |
} |
| 1408 |
} |
| 1409 |
if (status & IntReq) { /* Restore all interrupt sources. */ |
| 1410 |
outw(vp->status_enable, ioaddr + EL3_CMD); |
| 1411 |
outw(vp->intr_enable, ioaddr + EL3_CMD); |
| 1412 |
} |
| 1413 |
if (status & HostError) { |
| 1414 |
u16 fifo_diag; |
| 1415 |
EL3WINDOW(4); |
| 1416 |
fifo_diag = inw(ioaddr + Wn4_FIFODiag); |
| 1417 |
if (vortex_debug > 0) |
| 1418 |
printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n", |
| 1419 |
dev->name, fifo_diag); |
| 1420 |
/* Adapter failure requires Tx/Rx reset and reinit. */ |
| 1421 |
if (vp->full_bus_master_tx) { |
| 1422 |
outw(TotalReset | 0xff, ioaddr + EL3_CMD); |
| 1423 |
for (i = 2000; i >= 0 ; i--) |
| 1424 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1425 |
break; |
| 1426 |
/* Re-enable the receiver. */ |
| 1427 |
outw(RxEnable, ioaddr + EL3_CMD); |
| 1428 |
outw(TxEnable, ioaddr + EL3_CMD); |
| 1429 |
} else if (fifo_diag & 0x0400) |
| 1430 |
do_tx_reset = 1; |
| 1431 |
if (fifo_diag & 0x3000) { |
| 1432 |
outw(RxReset, ioaddr + EL3_CMD); |
| 1433 |
for (i = 2000; i >= 0 ; i--) |
| 1434 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1435 |
break; |
| 1436 |
/* Set the Rx filter to the current state. */ |
| 1437 |
set_rx_mode(dev); |
| 1438 |
outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */ |
| 1439 |
outw(AckIntr | HostError, ioaddr + EL3_CMD); |
| 1440 |
} |
| 1441 |
} |
| 1442 |
if (do_tx_reset) { |
| 1443 |
int j; |
| 1444 |
outw(TxReset, ioaddr + EL3_CMD); |
| 1445 |
for (j = 200; j >= 0 ; j--) |
| 1446 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1447 |
break; |
| 1448 |
outw(TxEnable, ioaddr + EL3_CMD); |
| 1449 |
} |
| 1450 |
|
| 1451 |
} |
| 1452 |
|
| 1453 |
|
| 1454 |
static int |
| 1455 |
vortex_start_xmit(struct sk_buff *skb, struct device *dev) |
| 1456 |
{ |
| 1457 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1458 |
long ioaddr = dev->base_addr; |
| 1459 |
|
| 1460 |
if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) { |
| 1461 |
if (jiffies - dev->trans_start >= TX_TIMEOUT) |
| 1462 |
vortex_tx_timeout(dev); |
| 1463 |
return 1; |
| 1464 |
} |
| 1465 |
|
| 1466 |
/* Put out the doubleword header... */ |
| 1467 |
outl(skb->len, ioaddr + TX_FIFO); |
| 1468 |
if (vp->bus_master) { |
| 1469 |
/* Set the bus-master controller to transfer the packet. */ |
| 1470 |
outl(virt_to_bus(skb->data), ioaddr + Wn7_MasterAddr); |
| 1471 |
outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); |
| 1472 |
vp->tx_skb = skb; |
| 1473 |
outw(StartDMADown, ioaddr + EL3_CMD); |
| 1474 |
/* dev->tbusy will be cleared at the DMADone interrupt. */ |
| 1475 |
} else { |
| 1476 |
/* ... and the packet rounded to a doubleword. */ |
| 1477 |
outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2); |
| 1478 |
DEV_FREE_SKB(skb); |
| 1479 |
if (inw(ioaddr + TxFree) > 1536) { |
| 1480 |
clear_bit(0, (void*)&dev->tbusy); |
| 1481 |
} else |
| 1482 |
/* Interrupt us when the FIFO has room for max-sized packet. */ |
| 1483 |
outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
| 1484 |
} |
| 1485 |
|
| 1486 |
dev->trans_start = jiffies; |
| 1487 |
|
| 1488 |
/* Clear the Tx status stack. */ |
| 1489 |
{ |
| 1490 |
int tx_status; |
| 1491 |
int i = 32; |
| 1492 |
|
| 1493 |
while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) { |
| 1494 |
if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */ |
| 1495 |
if (vortex_debug > 2) |
| 1496 |
printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n", |
| 1497 |
dev->name, tx_status); |
| 1498 |
if (tx_status & 0x04) vp->stats.tx_fifo_errors++; |
| 1499 |
if (tx_status & 0x38) vp->stats.tx_aborted_errors++; |
| 1500 |
if (tx_status & 0x30) { |
| 1501 |
int j; |
| 1502 |
outw(TxReset, ioaddr + EL3_CMD); |
| 1503 |
for (j = 200; j >= 0 ; j--) |
| 1504 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1505 |
break; |
| 1506 |
} |
| 1507 |
outw(TxEnable, ioaddr + EL3_CMD); |
| 1508 |
} |
| 1509 |
outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */ |
| 1510 |
} |
| 1511 |
} |
| 1512 |
return 0; |
| 1513 |
} |
| 1514 |
|
| 1515 |
static int |
| 1516 |
boomerang_start_xmit(struct sk_buff *skb, struct device *dev) |
| 1517 |
{ |
| 1518 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1519 |
long ioaddr = dev->base_addr; |
| 1520 |
|
| 1521 |
if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) { |
| 1522 |
if (jiffies - dev->trans_start >= TX_TIMEOUT) |
| 1523 |
vortex_tx_timeout(dev); |
| 1524 |
return 1; |
| 1525 |
} else { |
| 1526 |
/* Calculate the next Tx descriptor entry. */ |
| 1527 |
int entry = vp->cur_tx % TX_RING_SIZE; |
| 1528 |
struct boom_tx_desc *prev_entry = |
| 1529 |
&vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE]; |
| 1530 |
unsigned long flags; |
| 1531 |
int i; |
| 1532 |
|
| 1533 |
if (vortex_debug > 3) |
| 1534 |
printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n", |
| 1535 |
dev->name, vp->cur_tx); |
| 1536 |
if (vp->tx_full) { |
| 1537 |
if (vortex_debug >0) |
| 1538 |
printk(KERN_WARNING "%s: Tx Ring full, refusing to send buffer.\n", |
| 1539 |
dev->name); |
| 1540 |
return 1; |
| 1541 |
} |
| 1542 |
vp->tx_skbuff[entry] = skb; |
| 1543 |
vp->tx_ring[entry].next = 0; |
| 1544 |
vp->tx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->data)); |
| 1545 |
vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG); |
| 1546 |
vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); |
| 1547 |
|
| 1548 |
save_flags(flags); |
| 1549 |
cli(); |
| 1550 |
outw(DownStall, ioaddr + EL3_CMD); |
| 1551 |
/* Wait for the stall to complete. */ |
| 1552 |
for (i = 600; i >= 0 ; i--) |
| 1553 |
if ( (inw(ioaddr + EL3_STATUS) & CmdInProgress) == 0) |
| 1554 |
break; |
| 1555 |
prev_entry->next = cpu_to_le32(virt_to_bus(&vp->tx_ring[entry])); |
| 1556 |
if (inl(ioaddr + DownListPtr) == 0) { |
| 1557 |
outl(virt_to_bus(&vp->tx_ring[entry]), ioaddr + DownListPtr); |
| 1558 |
queued_packet++; |
| 1559 |
} |
| 1560 |
outw(DownUnstall, ioaddr + EL3_CMD); |
| 1561 |
restore_flags(flags); |
| 1562 |
|
| 1563 |
vp->cur_tx++; |
| 1564 |
if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) |
| 1565 |
vp->tx_full = 1; |
| 1566 |
else { /* Clear previous interrupt enable. */ |
| 1567 |
#if defined(tx_interrupt_mitigation) |
| 1568 |
prev_entry->status &= cpu_to_le32(~TxIntrUploaded); |
| 1569 |
#endif |
| 1570 |
clear_bit(0, (void*)&dev->tbusy); |
| 1571 |
} |
| 1572 |
dev->trans_start = jiffies; |
| 1573 |
return 0; |
| 1574 |
} |
| 1575 |
} |
| 1576 |
|
| 1577 |
/* The interrupt handler does all of the Rx thread work and cleans up |
| 1578 |
after the Tx thread. */ |
| 1579 |
static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
| 1580 |
{ |
| 1581 |
struct device *dev = dev_id; |
| 1582 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1583 |
long ioaddr; |
| 1584 |
int latency, status; |
| 1585 |
int work_done = max_interrupt_work; |
| 1586 |
|
| 1587 |
#if defined(__i386__) |
| 1588 |
/* A lock to prevent simultaneous entry bug on Intel SMP machines. */ |
| 1589 |
if (test_and_set_bit(0, (void*)&dev->interrupt)) { |
| 1590 |
printk(KERN_ERR"%s: SMP simultaneous entry of an interrupt handler.\n", |
| 1591 |
dev->name); |
| 1592 |
dev->interrupt = 0; /* Avoid halting machine. */ |
| 1593 |
return; |
| 1594 |
} |
| 1595 |
#else |
| 1596 |
if (dev->interrupt) { |
| 1597 |
printk(KERN_ERR "%s: Re-entering the interrupt handler.\n", dev->name); |
| 1598 |
return; |
| 1599 |
} |
| 1600 |
dev->interrupt = 1; |
| 1601 |
#endif |
| 1602 |
|
| 1603 |
dev->interrupt = 1; |
| 1604 |
ioaddr = dev->base_addr; |
| 1605 |
latency = inb(ioaddr + Timer); |
| 1606 |
status = inw(ioaddr + EL3_STATUS); |
| 1607 |
|
| 1608 |
if (status == 0xffff) |
| 1609 |
goto handler_exit; |
| 1610 |
if (vortex_debug > 4) |
| 1611 |
printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n", |
| 1612 |
dev->name, status, latency); |
| 1613 |
do { |
| 1614 |
if (vortex_debug > 5) |
| 1615 |
printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n", |
| 1616 |
dev->name, status); |
| 1617 |
if (status & RxComplete) |
| 1618 |
vortex_rx(dev); |
| 1619 |
if (status & UpComplete) { |
| 1620 |
outw(AckIntr | UpComplete, ioaddr + EL3_CMD); |
| 1621 |
boomerang_rx(dev); |
| 1622 |
} |
| 1623 |
|
| 1624 |
if (status & TxAvailable) { |
| 1625 |
if (vortex_debug > 5) |
| 1626 |
printk(KERN_DEBUG " TX room bit was handled.\n"); |
| 1627 |
/* There's room in the FIFO for a full-sized packet. */ |
| 1628 |
outw(AckIntr | TxAvailable, ioaddr + EL3_CMD); |
| 1629 |
clear_bit(0, (void*)&dev->tbusy); |
| 1630 |
mark_bh(NET_BH); |
| 1631 |
} |
| 1632 |
|
| 1633 |
if (status & DownComplete) { |
| 1634 |
unsigned int dirty_tx = vp->dirty_tx; |
| 1635 |
|
| 1636 |
outw(AckIntr | DownComplete, ioaddr + EL3_CMD); |
| 1637 |
while (vp->cur_tx - dirty_tx > 0) { |
| 1638 |
int entry = dirty_tx % TX_RING_SIZE; |
| 1639 |
if (inl(ioaddr + DownListPtr) == |
| 1640 |
virt_to_bus(&vp->tx_ring[entry])) |
| 1641 |
break; /* It still hasn't been processed. */ |
| 1642 |
if (vp->tx_skbuff[entry]) { |
| 1643 |
DEV_FREE_SKB(vp->tx_skbuff[entry]); |
| 1644 |
vp->tx_skbuff[entry] = 0; |
| 1645 |
} |
| 1646 |
/* vp->stats.tx_packets++; Counted below. */ |
| 1647 |
dirty_tx++; |
| 1648 |
} |
| 1649 |
vp->dirty_tx = dirty_tx; |
| 1650 |
if (vp->tx_full && (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) { |
| 1651 |
vp->tx_full = 0; |
| 1652 |
clear_bit(0, (void*)&dev->tbusy); |
| 1653 |
mark_bh(NET_BH); |
| 1654 |
} |
| 1655 |
} |
| 1656 |
if (status & DMADone) { |
| 1657 |
if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) { |
| 1658 |
outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */ |
| 1659 |
DEV_FREE_SKB(vp->tx_skb); /* Release the transfered buffer */ |
| 1660 |
if (inw(ioaddr + TxFree) > 1536) { |
| 1661 |
clear_bit(0, (void*)&dev->tbusy); |
| 1662 |
mark_bh(NET_BH); |
| 1663 |
} else /* Interrupt when FIFO has room for max-sized packet. */ |
| 1664 |
outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
| 1665 |
} |
| 1666 |
} |
| 1667 |
/* Check for all uncommon interrupts at once. */ |
| 1668 |
if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) { |
| 1669 |
if (status == 0xffff) |
| 1670 |
break; |
| 1671 |
vortex_error(dev, status); |
| 1672 |
} |
| 1673 |
|
| 1674 |
if (--work_done < 0) { |
| 1675 |
if ((status & (0x7fe - (UpComplete | DownComplete))) == 0) { |
| 1676 |
/* Just ack these and return. */ |
| 1677 |
outw(AckIntr | UpComplete | DownComplete, ioaddr + EL3_CMD); |
| 1678 |
} else { |
| 1679 |
printk(KERN_WARNING "%s: Too much work in interrupt, status " |
| 1680 |
"%4.4x. Temporarily disabling functions (%4.4x).\n", |
| 1681 |
dev->name, status, SetStatusEnb | ((~status) & 0x7FE)); |
| 1682 |
/* Disable all pending interrupts. */ |
| 1683 |
outw(SetStatusEnb | ((~status) & 0x7FE), ioaddr + EL3_CMD); |
| 1684 |
outw(AckIntr | 0x7FF, ioaddr + EL3_CMD); |
| 1685 |
/* The timer will reenable interrupts. */ |
| 1686 |
break; |
| 1687 |
} |
| 1688 |
} |
| 1689 |
/* Acknowledge the IRQ. */ |
| 1690 |
outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); |
| 1691 |
if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
| 1692 |
writel(0x8000, vp->cb_fn_base + 4); |
| 1693 |
|
| 1694 |
} while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete)); |
| 1695 |
|
| 1696 |
if (vortex_debug > 4) |
| 1697 |
printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n", |
| 1698 |
dev->name, status); |
| 1699 |
handler_exit: |
| 1700 |
#if defined(__i386__) |
| 1701 |
clear_bit(0, (void*)&dev->interrupt); |
| 1702 |
#else |
| 1703 |
dev->interrupt = 0; |
| 1704 |
#endif |
| 1705 |
return; |
| 1706 |
} |
| 1707 |
|
| 1708 |
static int vortex_rx(struct device *dev) |
| 1709 |
{ |
| 1710 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1711 |
long ioaddr = dev->base_addr; |
| 1712 |
int i; |
| 1713 |
short rx_status; |
| 1714 |
|
| 1715 |
if (vortex_debug > 5) |
| 1716 |
printk(KERN_DEBUG" In rx_packet(), status %4.4x, rx_status %4.4x.\n", |
| 1717 |
inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
| 1718 |
while ((rx_status = inw(ioaddr + RxStatus)) > 0) { |
| 1719 |
if (rx_status & 0x4000) { /* Error, update stats. */ |
| 1720 |
unsigned char rx_error = inb(ioaddr + RxErrors); |
| 1721 |
if (vortex_debug > 2) |
| 1722 |
printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error); |
| 1723 |
vp->stats.rx_errors++; |
| 1724 |
if (rx_error & 0x01) vp->stats.rx_over_errors++; |
| 1725 |
if (rx_error & 0x02) vp->stats.rx_length_errors++; |
| 1726 |
if (rx_error & 0x04) vp->stats.rx_frame_errors++; |
| 1727 |
if (rx_error & 0x08) vp->stats.rx_crc_errors++; |
| 1728 |
if (rx_error & 0x10) vp->stats.rx_length_errors++; |
| 1729 |
} else { |
| 1730 |
/* The packet length: up to 4.5K!. */ |
| 1731 |
int pkt_len = rx_status & 0x1fff; |
| 1732 |
struct sk_buff *skb; |
| 1733 |
|
| 1734 |
skb = dev_alloc_skb(pkt_len + 5); |
| 1735 |
if (vortex_debug > 4) |
| 1736 |
printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n", |
| 1737 |
pkt_len, rx_status); |
| 1738 |
if (skb != NULL) { |
| 1739 |
skb->dev = dev; |
| 1740 |
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
| 1741 |
/* 'skb_put()' points to the start of sk_buff data area. */ |
| 1742 |
if (vp->bus_master && |
| 1743 |
! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) { |
| 1744 |
outl(virt_to_bus(skb_put(skb, pkt_len)), |
| 1745 |
ioaddr + Wn7_MasterAddr); |
| 1746 |
outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); |
| 1747 |
outw(StartDMAUp, ioaddr + EL3_CMD); |
| 1748 |
while (inw(ioaddr + Wn7_MasterStatus) & 0x8000) |
| 1749 |
; |
| 1750 |
} else { |
| 1751 |
insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len), |
| 1752 |
(pkt_len + 3) >> 2); |
| 1753 |
} |
| 1754 |
outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */ |
| 1755 |
skb->protocol = eth_type_trans(skb, dev); |
| 1756 |
netif_rx(skb); |
| 1757 |
dev->last_rx = jiffies; |
| 1758 |
vp->stats.rx_packets++; |
| 1759 |
/* Wait a limited time to go to next packet. */ |
| 1760 |
for (i = 200; i >= 0; i--) |
| 1761 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1762 |
break; |
| 1763 |
continue; |
| 1764 |
} else if (vortex_debug) |
| 1765 |
printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of " |
| 1766 |
"size %d.\n", dev->name, pkt_len); |
| 1767 |
} |
| 1768 |
outw(RxDiscard, ioaddr + EL3_CMD); |
| 1769 |
vp->stats.rx_dropped++; |
| 1770 |
/* Wait a limited time to skip this packet. */ |
| 1771 |
for (i = 200; i >= 0; i--) |
| 1772 |
if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
| 1773 |
break; |
| 1774 |
} |
| 1775 |
|
| 1776 |
return 0; |
| 1777 |
} |
| 1778 |
|
| 1779 |
static int |
| 1780 |
boomerang_rx(struct device *dev) |
| 1781 |
{ |
| 1782 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1783 |
int entry = vp->cur_rx % RX_RING_SIZE; |
| 1784 |
long ioaddr = dev->base_addr; |
| 1785 |
int rx_status; |
| 1786 |
int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx; |
| 1787 |
|
| 1788 |
if (vortex_debug > 5) |
| 1789 |
printk(KERN_DEBUG " In boomerang_rx(), status %4.4x, rx_status " |
| 1790 |
"%4.4x.\n", |
| 1791 |
inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
| 1792 |
while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){ |
| 1793 |
if (--rx_work_limit < 0) |
| 1794 |
break; |
| 1795 |
if (rx_status & RxDError) { /* Error, update stats. */ |
| 1796 |
unsigned char rx_error = rx_status >> 16; |
| 1797 |
if (vortex_debug > 2) |
| 1798 |
printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error); |
| 1799 |
vp->stats.rx_errors++; |
| 1800 |
if (rx_error & 0x01) vp->stats.rx_over_errors++; |
| 1801 |
if (rx_error & 0x02) vp->stats.rx_length_errors++; |
| 1802 |
if (rx_error & 0x04) vp->stats.rx_frame_errors++; |
| 1803 |
if (rx_error & 0x08) vp->stats.rx_crc_errors++; |
| 1804 |
if (rx_error & 0x10) vp->stats.rx_length_errors++; |
| 1805 |
} else { |
| 1806 |
/* The packet length: up to 4.5K!. */ |
| 1807 |
int pkt_len = rx_status & 0x1fff; |
| 1808 |
struct sk_buff *skb; |
| 1809 |
|
| 1810 |
if (vortex_debug > 4) |
| 1811 |
printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n", |
| 1812 |
pkt_len, rx_status); |
| 1813 |
|
| 1814 |
/* Check if the packet is long enough to just accept without |
| 1815 |
copying to a properly sized skbuff. */ |
| 1816 |
if (pkt_len < rx_copybreak |
| 1817 |
&& (skb = dev_alloc_skb(pkt_len + 2)) != 0) { |
| 1818 |
skb->dev = dev; |
| 1819 |
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
| 1820 |
/* 'skb_put()' points to the start of sk_buff data area. */ |
| 1821 |
memcpy(skb_put(skb, pkt_len), |
| 1822 |
bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)), |
| 1823 |
pkt_len); |
| 1824 |
rx_copy++; |
| 1825 |
} else { |
| 1826 |
void *temp; |
| 1827 |
/* Pass up the skbuff already on the Rx ring. */ |
| 1828 |
skb = vp->rx_skbuff[entry]; |
| 1829 |
vp->rx_skbuff[entry] = NULL; |
| 1830 |
temp = skb_put(skb, pkt_len); |
| 1831 |
/* Remove this checking code for final release. */ |
| 1832 |
if (bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)) != temp) |
| 1833 |
printk(KERN_ERR "%s: Warning -- the skbuff addresses do not match" |
| 1834 |
" in boomerang_rx: %p vs. %p.\n", dev->name, |
| 1835 |
bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)), |
| 1836 |
temp); |
| 1837 |
rx_nocopy++; |
| 1838 |
} |
| 1839 |
skb->protocol = eth_type_trans(skb, dev); |
| 1840 |
{ /* Use hardware checksum info. */ |
| 1841 |
int csum_bits = rx_status & 0xee000000; |
| 1842 |
if (csum_bits && |
| 1843 |
(csum_bits == (IPChksumValid | TCPChksumValid) || |
| 1844 |
csum_bits == (IPChksumValid | UDPChksumValid))) { |
| 1845 |
skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1846 |
rx_csumhits++; |
| 1847 |
} |
| 1848 |
} |
| 1849 |
netif_rx(skb); |
| 1850 |
dev->last_rx = jiffies; |
| 1851 |
vp->stats.rx_packets++; |
| 1852 |
} |
| 1853 |
entry = (++vp->cur_rx) % RX_RING_SIZE; |
| 1854 |
} |
| 1855 |
/* Refill the Rx ring buffers. */ |
| 1856 |
for (; vp->dirty_rx < vp->cur_rx; vp->dirty_rx++) { |
| 1857 |
struct sk_buff *skb; |
| 1858 |
entry = vp->dirty_rx % RX_RING_SIZE; |
| 1859 |
if (vp->rx_skbuff[entry] == NULL) { |
| 1860 |
skb = dev_alloc_skb(PKT_BUF_SZ); |
| 1861 |
if (skb == NULL) |
| 1862 |
break; /* Bad news! */ |
| 1863 |
skb->dev = dev; /* Mark as being used by this device. */ |
| 1864 |
skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
| 1865 |
vp->rx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->tail)); |
| 1866 |
vp->rx_skbuff[entry] = skb; |
| 1867 |
} |
| 1868 |
vp->rx_ring[entry].status = 0; /* Clear complete bit. */ |
| 1869 |
outw(UpUnstall, ioaddr + EL3_CMD); |
| 1870 |
} |
| 1871 |
return 0; |
| 1872 |
} |
| 1873 |
|
| 1874 |
static int |
| 1875 |
vortex_close(struct device *dev) |
| 1876 |
{ |
| 1877 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1878 |
long ioaddr = dev->base_addr; |
| 1879 |
int i; |
| 1880 |
|
| 1881 |
dev->start = 0; |
| 1882 |
dev->tbusy = 1; |
| 1883 |
|
| 1884 |
if (vortex_debug > 1) { |
| 1885 |
printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n", |
| 1886 |
dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus)); |
| 1887 |
printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d" |
| 1888 |
" tx_queued %d Rx pre-checksummed %d.\n", |
| 1889 |
dev->name, rx_nocopy, rx_copy, queued_packet, rx_csumhits); |
| 1890 |
} |
| 1891 |
|
| 1892 |
del_timer(&vp->timer); |
| 1893 |
|
| 1894 |
/* Turn off statistics ASAP. We update vp->stats below. */ |
| 1895 |
outw(StatsDisable, ioaddr + EL3_CMD); |
| 1896 |
|
| 1897 |
/* Disable the receiver and transmitter. */ |
| 1898 |
outw(RxDisable, ioaddr + EL3_CMD); |
| 1899 |
outw(TxDisable, ioaddr + EL3_CMD); |
| 1900 |
|
| 1901 |
if (dev->if_port == XCVR_10base2) |
| 1902 |
/* Turn off thinnet power. Green! */ |
| 1903 |
outw(StopCoax, ioaddr + EL3_CMD); |
| 1904 |
|
| 1905 |
free_irq(dev->irq, dev); |
| 1906 |
|
| 1907 |
outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD); |
| 1908 |
|
| 1909 |
update_stats(ioaddr, dev); |
| 1910 |
if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */ |
| 1911 |
outl(0, ioaddr + UpListPtr); |
| 1912 |
for (i = 0; i < RX_RING_SIZE; i++) |
| 1913 |
if (vp->rx_skbuff[i]) { |
| 1914 |
#if LINUX_VERSION_CODE < 0x20100 |
| 1915 |
vp->rx_skbuff[i]->free = 1; |
| 1916 |
#endif |
| 1917 |
DEV_FREE_SKB(vp->rx_skbuff[i]); |
| 1918 |
vp->rx_skbuff[i] = 0; |
| 1919 |
} |
| 1920 |
} |
| 1921 |
if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */ |
| 1922 |
outl(0, ioaddr + DownListPtr); |
| 1923 |
for (i = 0; i < TX_RING_SIZE; i++) |
| 1924 |
if (vp->tx_skbuff[i]) { |
| 1925 |
DEV_FREE_SKB(vp->tx_skbuff[i]); |
| 1926 |
vp->tx_skbuff[i] = 0; |
| 1927 |
} |
| 1928 |
} |
| 1929 |
|
| 1930 |
if (vp->capabilities & CapPwrMgmt) |
| 1931 |
acpi_set_WOL(dev); |
| 1932 |
MOD_DEC_USE_COUNT; |
| 1933 |
|
| 1934 |
return 0; |
| 1935 |
} |
| 1936 |
|
| 1937 |
static struct net_device_stats *vortex_get_stats(struct device *dev) |
| 1938 |
{ |
| 1939 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1940 |
unsigned long flags; |
| 1941 |
|
| 1942 |
if (dev->start) { |
| 1943 |
save_flags(flags); |
| 1944 |
cli(); |
| 1945 |
update_stats(dev->base_addr, dev); |
| 1946 |
restore_flags(flags); |
| 1947 |
} |
| 1948 |
return &vp->stats; |
| 1949 |
} |
| 1950 |
|
| 1951 |
/* Update statistics. |
| 1952 |
Unlike with the EL3 we need not worry about interrupts changing |
| 1953 |
the window setting from underneath us, but we must still guard |
| 1954 |
against a race condition with a StatsUpdate interrupt updating the |
| 1955 |
table. This is done by checking that the ASM (!) code generated uses |
| 1956 |
atomic updates with '+='. |
| 1957 |
*/ |
| 1958 |
static void update_stats(long ioaddr, struct device *dev) |
| 1959 |
{ |
| 1960 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 1961 |
int old_window = inw(ioaddr + EL3_CMD); |
| 1962 |
|
| 1963 |
if (old_window == 0xffff) /* Chip suspended or ejected. */ |
| 1964 |
return; |
| 1965 |
/* Unlike the 3c5x9 we need not turn off stats updates while reading. */ |
| 1966 |
/* Switch to the stats window, and read everything. */ |
| 1967 |
EL3WINDOW(6); |
| 1968 |
vp->stats.tx_carrier_errors += inb(ioaddr + 0); |
| 1969 |
vp->stats.tx_heartbeat_errors += inb(ioaddr + 1); |
| 1970 |
/* Multiple collisions. */ inb(ioaddr + 2); |
| 1971 |
vp->stats.collisions += inb(ioaddr + 3); |
| 1972 |
vp->stats.tx_window_errors += inb(ioaddr + 4); |
| 1973 |
vp->stats.rx_fifo_errors += inb(ioaddr + 5); |
| 1974 |
vp->stats.tx_packets += inb(ioaddr + 6); |
| 1975 |
vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4; |
| 1976 |
/* Rx packets */ inb(ioaddr + 7); /* Must read to clear */ |
| 1977 |
/* Tx deferrals */ inb(ioaddr + 8); |
| 1978 |
/* Don't bother with register 9, an extension of registers 6&7. |
| 1979 |
If we do use the 6&7 values the atomic update assumption above |
| 1980 |
is invalid. */ |
| 1981 |
#if LINUX_VERSION_CODE > 0x020119 |
| 1982 |
vp->stats.rx_bytes += inw(ioaddr + 10); |
| 1983 |
vp->stats.tx_bytes += inw(ioaddr + 12); |
| 1984 |
#else |
| 1985 |
inw(ioaddr + 10); |
| 1986 |
inw(ioaddr + 12); |
| 1987 |
#endif |
| 1988 |
/* New: On the Vortex we must also clear the BadSSD counter. */ |
| 1989 |
EL3WINDOW(4); |
| 1990 |
inb(ioaddr + 12); |
| 1991 |
|
| 1992 |
/* We change back to window 7 (not 1) with the Vortex. */ |
| 1993 |
EL3WINDOW(old_window >> 13); |
| 1994 |
return; |
| 1995 |
} |
| 1996 |
|
| 1997 |
static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd) |
| 1998 |
{ |
| 1999 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 2000 |
long ioaddr = dev->base_addr; |
| 2001 |
u16 *data = (u16 *)&rq->ifr_data; |
| 2002 |
int phy = vp->phys[0] & 0x1f; |
| 2003 |
|
| 2004 |
switch(cmd) { |
| 2005 |
case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ |
| 2006 |
data[0] = phy; |
| 2007 |
case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ |
| 2008 |
EL3WINDOW(4); |
| 2009 |
data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f); |
| 2010 |
return 0; |
| 2011 |
case SIOCDEVPRIVATE+2: /* Write the specified MII register */ |
| 2012 |
if (!capable(CAP_NET_ADMIN)) |
| 2013 |
return -EPERM; |
| 2014 |
EL3WINDOW(4); |
| 2015 |
mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]); |
| 2016 |
return 0; |
| 2017 |
default: |
| 2018 |
return -EOPNOTSUPP; |
| 2019 |
} |
| 2020 |
} |
| 2021 |
|
| 2022 |
/* Pre-Cyclone chips have no documented multicast filter, so the only |
| 2023 |
multicast setting is to receive all multicast frames. At least |
| 2024 |
the chip has a very clean way to set the mode, unlike many others. */ |
| 2025 |
static void set_rx_mode(struct device *dev) |
| 2026 |
{ |
| 2027 |
long ioaddr = dev->base_addr; |
| 2028 |
int new_mode; |
| 2029 |
|
| 2030 |
if (dev->flags & IFF_PROMISC) { |
| 2031 |
if (vortex_debug > 0) |
| 2032 |
printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name); |
| 2033 |
new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm; |
| 2034 |
} else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) { |
| 2035 |
new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast; |
| 2036 |
} else |
| 2037 |
new_mode = SetRxFilter | RxStation | RxBroadcast; |
| 2038 |
|
| 2039 |
outw(new_mode, ioaddr + EL3_CMD); |
| 2040 |
} |
| 2041 |
|
| 2042 |
|
| 2043 |
/* MII transceiver control section. |
| 2044 |
Read and write the MII registers using software-generated serial |
| 2045 |
MDIO protocol. See the MII specifications or DP83840A data sheet |
| 2046 |
for details. */ |
| 2047 |
|
| 2048 |
/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually |
| 2049 |
met by back-to-back PCI I/O cycles, but we insert a delay to avoid |
| 2050 |
"overclocking" issues. */ |
| 2051 |
#define mdio_delay() inl(mdio_addr) |
| 2052 |
|
| 2053 |
#define MDIO_SHIFT_CLK 0x01 |
| 2054 |
#define MDIO_DIR_WRITE 0x04 |
| 2055 |
#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE) |
| 2056 |
#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE) |
| 2057 |
#define MDIO_DATA_READ 0x02 |
| 2058 |
#define MDIO_ENB_IN 0x00 |
| 2059 |
|
| 2060 |
/* Generate the preamble required for initial synchronization and |
| 2061 |
a few older transceivers. */ |
| 2062 |
static void mdio_sync(long ioaddr, int bits) |
| 2063 |
{ |
| 2064 |
long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
| 2065 |
|
| 2066 |
/* Establish sync by sending at least 32 logic ones. */ |
| 2067 |
while (-- bits >= 0) { |
| 2068 |
outw(MDIO_DATA_WRITE1, mdio_addr); |
| 2069 |
mdio_delay(); |
| 2070 |
outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); |
| 2071 |
mdio_delay(); |
| 2072 |
} |
| 2073 |
} |
| 2074 |
|
| 2075 |
static int mdio_read(long ioaddr, int phy_id, int location) |
| 2076 |
{ |
| 2077 |
int i; |
| 2078 |
int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; |
| 2079 |
unsigned int retval = 0; |
| 2080 |
long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
| 2081 |
|
| 2082 |
if (mii_preamble_required) |
| 2083 |
mdio_sync(ioaddr, 32); |
| 2084 |
|
| 2085 |
/* Shift the read command bits out. */ |
| 2086 |
for (i = 14; i >= 0; i--) { |
| 2087 |
int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; |
| 2088 |
outw(dataval, mdio_addr); |
| 2089 |
mdio_delay(); |
| 2090 |
outw(dataval | MDIO_SHIFT_CLK, mdio_addr); |
| 2091 |
mdio_delay(); |
| 2092 |
} |
| 2093 |
/* Read the two transition, 16 data, and wire-idle bits. */ |
| 2094 |
for (i = 19; i > 0; i--) { |
| 2095 |
outw(MDIO_ENB_IN, mdio_addr); |
| 2096 |
mdio_delay(); |
| 2097 |
retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); |
| 2098 |
outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); |
| 2099 |
mdio_delay(); |
| 2100 |
} |
| 2101 |
#if 0 |
| 2102 |
return (retval>>1) & 0x1ffff; |
| 2103 |
#else |
| 2104 |
return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; |
| 2105 |
#endif |
| 2106 |
} |
| 2107 |
|
| 2108 |
static void mdio_write(long ioaddr, int phy_id, int location, int value) |
| 2109 |
{ |
| 2110 |
int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; |
| 2111 |
long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
| 2112 |
int i; |
| 2113 |
|
| 2114 |
if (mii_preamble_required) |
| 2115 |
mdio_sync(ioaddr, 32); |
| 2116 |
|
| 2117 |
/* Shift the command bits out. */ |
| 2118 |
for (i = 31; i >= 0; i--) { |
| 2119 |
int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; |
| 2120 |
outw(dataval, mdio_addr); |
| 2121 |
mdio_delay(); |
| 2122 |
outw(dataval | MDIO_SHIFT_CLK, mdio_addr); |
| 2123 |
mdio_delay(); |
| 2124 |
} |
| 2125 |
/* Leave the interface idle. */ |
| 2126 |
for (i = 1; i >= 0; i--) { |
| 2127 |
outw(MDIO_ENB_IN, mdio_addr); |
| 2128 |
mdio_delay(); |
| 2129 |
outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); |
| 2130 |
mdio_delay(); |
| 2131 |
} |
| 2132 |
|
| 2133 |
return; |
| 2134 |
} |
| 2135 |
|
| 2136 |
/* ACPI: Advanced Configuration and Power Interface. */ |
| 2137 |
/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */ |
| 2138 |
static void acpi_set_WOL(struct device *dev) |
| 2139 |
{ |
| 2140 |
struct vortex_private *vp = (struct vortex_private *)dev->priv; |
| 2141 |
long ioaddr = dev->base_addr; |
| 2142 |
|
| 2143 |
/* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ |
| 2144 |
EL3WINDOW(7); |
| 2145 |
outw(2, ioaddr + 0x0c); |
| 2146 |
/* The RxFilter must accept the WOL frames. */ |
| 2147 |
outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD); |
| 2148 |
outw(RxEnable, ioaddr + EL3_CMD); |
| 2149 |
/* Change the power state to D3; RxEnable doesn't take effect. */ |
| 2150 |
pcibios_write_config_word(vp->pci_bus, vp->pci_devfn, 0xe0, 0x8103); |
| 2151 |
} |
| 2152 |
/* Change from D3 (sleep) to D0 (active). |
| 2153 |
Problem: The Cyclone forgets all PCI config info during the transition! */ |
| 2154 |
static void acpi_wake(int bus, int devfn) |
| 2155 |
{ |
| 2156 |
u32 base0, base1, romaddr; |
| 2157 |
u16 pci_command, pwr_command; |
| 2158 |
u8 pci_latency, pci_cacheline, irq; |
| 2159 |
|
| 2160 |
pcibios_read_config_word(bus, devfn, 0xe0, &pwr_command); |
| 2161 |
if ((pwr_command & 3) == 0) |
| 2162 |
return; |
| 2163 |
pcibios_read_config_word( bus, devfn, PCI_COMMAND, &pci_command); |
| 2164 |
pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &base0); |
| 2165 |
pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_1, &base1); |
| 2166 |
pcibios_read_config_dword(bus, devfn, PCI_ROM_ADDRESS, &romaddr); |
| 2167 |
pcibios_read_config_byte( bus, devfn, PCI_LATENCY_TIMER, &pci_latency); |
| 2168 |
pcibios_read_config_byte( bus, devfn, PCI_CACHE_LINE_SIZE, &pci_cacheline); |
| 2169 |
pcibios_read_config_byte( bus, devfn, PCI_INTERRUPT_LINE, &irq); |
| 2170 |
|
| 2171 |
pcibios_write_config_word( bus, devfn, 0xe0, 0x0000); |
| 2172 |
pcibios_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, base0); |
| 2173 |
pcibios_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_1, base1); |
| 2174 |
pcibios_write_config_dword(bus, devfn, PCI_ROM_ADDRESS, romaddr); |
| 2175 |
pcibios_write_config_byte( bus, devfn, PCI_INTERRUPT_LINE, irq); |
| 2176 |
pcibios_write_config_byte( bus, devfn, PCI_LATENCY_TIMER, pci_latency); |
| 2177 |
pcibios_write_config_byte( bus, devfn, PCI_CACHE_LINE_SIZE, pci_cacheline); |
| 2178 |
pcibios_write_config_word( bus, devfn, PCI_COMMAND, pci_command | 5); |
| 2179 |
} |
| 2180 |
|
| 2181 |
|
| 2182 |
#ifdef MODULE |
| 2183 |
void cleanup_module(void) |
| 2184 |
{ |
| 2185 |
struct device *next_dev; |
| 2186 |
|
| 2187 |
#ifdef CARDBUS |
| 2188 |
unregister_driver(&vortex_ops); |
| 2189 |
#endif |
| 2190 |
|
| 2191 |
/* No need to check MOD_IN_USE, as sys_delete_module() checks. */ |
| 2192 |
while (root_vortex_dev) { |
| 2193 |
struct vortex_private *vp=(void *)(root_vortex_dev->priv); |
| 2194 |
next_dev = vp->next_module; |
| 2195 |
unregister_netdev(root_vortex_dev); |
| 2196 |
outw(TotalReset, root_vortex_dev->base_addr + EL3_CMD); |
| 2197 |
release_region(root_vortex_dev->base_addr, |
| 2198 |
pci_tbl[vp->chip_id].io_size); |
| 2199 |
kfree(root_vortex_dev); |
| 2200 |
kfree(vp->priv_addr); |
| 2201 |
root_vortex_dev = next_dev; |
| 2202 |
} |
| 2203 |
} |
| 2204 |
|
| 2205 |
#endif /* MODULE */ |
| 2206 |
|
| 2207 |
/* |
| 2208 |
* Local variables: |
| 2209 |
* compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`" |
| 2210 |
* SMP-compile-command: "gcc -D__SMP__ -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c" |
| 2211 |
* cardbus-compile-command: "gcc -DCARDBUS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c -o 3c575_cb.o -I/usr/src/linux/pcmcia-cs-3.0.9/include/" |
| 2212 |
* c-indent-level: 4 |
| 2213 |
* c-basic-offset: 4 |
| 2214 |
* tab-width: 4 |
| 2215 |
* End: |
| 2216 |
*/ |