| 77 |
|
|
| 78 |
#define MAX_BREAKPOINTS 32 |
#define MAX_BREAKPOINTS 32 |
| 79 |
|
|
| 80 |
|
#define TB_JMP_CACHE_BITS 12 |
| 81 |
|
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
| 82 |
|
|
| 83 |
#define CPU_TLB_SIZE 256 |
#define CPU_TLB_SIZE 256 |
| 84 |
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|
| 85 |
typedef struct CPUTLBEntry { |
typedef struct CPUTLBEntry { |
| 94 |
target_phys_addr_t addend; |
target_phys_addr_t addend; |
| 95 |
} CPUTLBEntry; |
} CPUTLBEntry; |
| 96 |
|
|
| 97 |
|
#define CPU_COMMON \ |
| 98 |
|
struct TranslationBlock *current_tb; /* currently executing TB */ \ |
| 99 |
|
/* soft mmu support */ \ |
| 100 |
|
/* in order to avoid passing too many arguments to the memory \ |
| 101 |
|
write helpers, we store some rarely used information in the CPU \ |
| 102 |
|
context) */ \ |
| 103 |
|
unsigned long mem_write_pc; /* host pc at which the memory was \ |
| 104 |
|
written */ \ |
| 105 |
|
target_ulong mem_write_vaddr; /* target virtual addr at which the \ |
| 106 |
|
memory was written */ \ |
| 107 |
|
/* 0 = kernel, 1 = user */ \ |
| 108 |
|
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; \ |
| 109 |
|
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; \ |
| 110 |
|
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
| 111 |
|
\ |
| 112 |
|
/* from this point: preserved by CPU reset */ \ |
| 113 |
|
/* ice debug support */ \ |
| 114 |
|
target_ulong breakpoints[MAX_BREAKPOINTS]; \ |
| 115 |
|
int nb_breakpoints; \ |
| 116 |
|
int singlestep_enabled; \ |
| 117 |
|
\ |
| 118 |
|
/* user data */ \ |
| 119 |
|
void *opaque; |
| 120 |
|
|
| 121 |
|
|
| 122 |
|
|
| 123 |
#endif |
#endif |