/[qemu]/qemu/cpu-exec.c
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revision 1.70 by bellard, Mon Dec 5 19:59:05 2005 UTC revision 1.71 by bellard, Mon Dec 5 20:31:52 2005 UTC
# Line 274  int cpu_exec(CPUState *env1) Line 274  int cpu_exec(CPUState *env1)
274              return EXCP_HALTED;              return EXCP_HALTED;
275          }          }
276      }      }
277    #elif defined(TARGET_SPARC)
278        if (env1->halted) {
279            if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
280                (env1->psret != 0)) {
281                env1->halted = 0;
282            } else {
283                return EXCP_HALTED;
284            }
285        }
286  #elif defined(TARGET_ARM)  #elif defined(TARGET_ARM)
287      if (env1->halted) {      if (env1->halted) {
288          /* An interrupt wakes the CPU even if the I and F CPSR bits are          /* An interrupt wakes the CPU even if the I and F CPSR bits are
# Line 522  int cpu_exec(CPUState *env1) Line 531  int cpu_exec(CPUState *env1)
531                      } else if (interrupt_request & CPU_INTERRUPT_TIMER) {                      } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
532                          //do_interrupt(0, 0, 0, 0, 0);                          //do_interrupt(0, 0, 0, 0, 0);
533                          env->interrupt_request &= ~CPU_INTERRUPT_TIMER;                          env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
534                      }                      } else if (interrupt_request & CPU_INTERRUPT_HALT) {
535                            env1->halted = 1;
536                            return EXCP_HALTED;
537                        }
538  #elif defined(TARGET_ARM)  #elif defined(TARGET_ARM)
539                      if (interrupt_request & CPU_INTERRUPT_FIQ                      if (interrupt_request & CPU_INTERRUPT_FIQ
540                          && !(env->uncached_cpsr & CPSR_F)) {                          && !(env->uncached_cpsr & CPSR_F)) {

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