| 305 |
int parent_irq; |
int parent_irq; |
| 306 |
} icp_pic_state; |
} icp_pic_state; |
| 307 |
|
|
|
static void icp_pic_set_level(icp_pic_state *, int, int); |
|
|
|
|
| 308 |
static void icp_pic_update(icp_pic_state *s) |
static void icp_pic_update(icp_pic_state *s) |
| 309 |
{ |
{ |
| 310 |
CPUState *env; |
CPUState *env; |
| 312 |
uint32_t flags; |
uint32_t flags; |
| 313 |
|
|
| 314 |
flags = (s->level & s->irq_enabled); |
flags = (s->level & s->irq_enabled); |
| 315 |
icp_pic_set_level((icp_pic_state *)s->parent, s->parent_irq, |
pic_set_irq_new(s->parent, s->parent_irq, |
| 316 |
flags != 0); |
flags != 0); |
| 317 |
return; |
return; |
| 318 |
} |
} |
| 319 |
/* Raise CPU interrupt. */ |
/* Raise CPU interrupt. */ |
| 330 |
} |
} |
| 331 |
} |
} |
| 332 |
|
|
| 333 |
static void icp_pic_set_level(icp_pic_state *s, int n, int level) |
void pic_set_irq_new(void *opaque, int irq, int level) |
| 334 |
{ |
{ |
| 335 |
|
icp_pic_state *s = (icp_pic_state *)opaque; |
| 336 |
if (level) |
if (level) |
| 337 |
s->level |= 1 << n; |
s->level |= 1 << irq; |
| 338 |
else |
else |
| 339 |
s->level &= ~(1 << n); |
s->level &= ~(1 << irq); |
| 340 |
icp_pic_update(s); |
icp_pic_update(s); |
| 341 |
} |
} |
| 342 |
|
|
| 384 |
break; |
break; |
| 385 |
case 4: /* INT_SOFTSET */ |
case 4: /* INT_SOFTSET */ |
| 386 |
if (value & 1) |
if (value & 1) |
| 387 |
icp_pic_set_level(s, 0, 1); |
pic_set_irq_new(s, 0, 1); |
| 388 |
break; |
break; |
| 389 |
case 5: /* INT_SOFTCLR */ |
case 5: /* INT_SOFTCLR */ |
| 390 |
if (value & 1) |
if (value & 1) |
| 391 |
icp_pic_set_level(s, 0, 0); |
pic_set_irq_new(s, 0, 0); |
| 392 |
break; |
break; |
| 393 |
case 10: /* FRQ_ENABLESET */ |
case 10: /* FRQ_ENABLESET */ |
| 394 |
s->fiq_enabled |= value; |
s->fiq_enabled |= value; |
| 512 |
/* Update interrupts. */ |
/* Update interrupts. */ |
| 513 |
for (n = 0; n < 3; n++) { |
for (n = 0; n < 3; n++) { |
| 514 |
if (s->int_level[n] && (s->control[n] & 0x20)) { |
if (s->int_level[n] && (s->control[n] & 0x20)) { |
| 515 |
icp_pic_set_level(s->pic, 5 + n, 1); |
pic_set_irq_new(s->pic, 5 + n, 1); |
| 516 |
} else { |
} else { |
| 517 |
icp_pic_set_level(s->pic, 5 + n, 0); |
pic_set_irq_new(s->pic, 5 + n, 0); |
| 518 |
} |
} |
| 519 |
if (next - s->expires[n] < 0) |
if (next - s->expires[n] < 0) |
| 520 |
next = s->expires[n]; |
next = s->expires[n]; |
| 730 |
uint32_t flags; |
uint32_t flags; |
| 731 |
|
|
| 732 |
flags = s->int_level & s->int_enabled; |
flags = s->int_level & s->int_enabled; |
| 733 |
icp_pic_set_level(s->pic, s->irq, flags != 0); |
pic_set_irq_new(s->pic, s->irq, flags != 0); |
| 734 |
} |
} |
| 735 |
|
|
| 736 |
static uint32_t pl011_read(void *opaque, target_phys_addr_t offset) |
static uint32_t pl011_read(void *opaque, target_phys_addr_t offset) |
| 1019 |
s->pending = level; |
s->pending = level; |
| 1020 |
raise = (s->pending && (s->cr & 0x10) != 0) |
raise = (s->pending && (s->cr & 0x10) != 0) |
| 1021 |
|| (s->cr & 0x08) != 0; |
|| (s->cr & 0x08) != 0; |
| 1022 |
icp_pic_set_level(s->pic, s->irq, raise); |
pic_set_irq_new(s->pic, s->irq, raise); |
| 1023 |
} |
} |
| 1024 |
|
|
| 1025 |
static uint32_t icp_kmi_read(void *opaque, target_phys_addr_t offset) |
static uint32_t icp_kmi_read(void *opaque, target_phys_addr_t offset) |
| 1195 |
icp_control_init(0xcb000000); |
icp_control_init(0xcb000000); |
| 1196 |
icp_kmi_init(0x18000000, pic, 3, 0); |
icp_kmi_init(0x18000000, pic, 3, 0); |
| 1197 |
icp_kmi_init(0x19000000, pic, 4, 1); |
icp_kmi_init(0x19000000, pic, 4, 1); |
| 1198 |
|
if (nd_table[0].vlan) |
| 1199 |
|
smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); |
| 1200 |
|
|
| 1201 |
/* Load the kernel. */ |
/* Load the kernel. */ |
| 1202 |
if (!kernel_filename) { |
if (!kernel_filename) { |