| 99 |
static void pic_irq_request(void *opaque, int level) |
static void pic_irq_request(void *opaque, int level) |
| 100 |
{ |
{ |
| 101 |
if (level) |
if (level) |
| 102 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
| 103 |
else |
else |
| 104 |
cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); |
| 105 |
} |
} |
| 106 |
|
|
| 107 |
/* PCI intack register */ |
/* PCI intack register */ |
| 294 |
/* Special port 92 */ |
/* Special port 92 */ |
| 295 |
/* Check soft reset asked */ |
/* Check soft reset asked */ |
| 296 |
if (val & 0x01) { |
if (val & 0x01) { |
| 297 |
// cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET); |
// cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET); |
| 298 |
} |
} |
| 299 |
/* Check LE mode */ |
/* Check LE mode */ |
| 300 |
if (val & 0x02) { |
if (val & 0x02) { |
| 331 |
break; |
break; |
| 332 |
case 0x0814: |
case 0x0814: |
| 333 |
/* L2 invalidate register */ |
/* L2 invalidate register */ |
| 334 |
// tlb_flush(cpu_single_env, 1); |
// tlb_flush(first_cpu, 1); |
| 335 |
break; |
break; |
| 336 |
case 0x081C: |
case 0x081C: |
| 337 |
/* system control register */ |
/* system control register */ |
| 523 |
const char *kernel_filename, const char *kernel_cmdline, |
const char *kernel_filename, const char *kernel_cmdline, |
| 524 |
const char *initrd_filename) |
const char *initrd_filename) |
| 525 |
{ |
{ |
| 526 |
|
CPUState *env; |
| 527 |
char buf[1024]; |
char buf[1024]; |
| 528 |
m48t59_t *nvram; |
m48t59_t *nvram; |
| 529 |
int PPC_io_memory; |
int PPC_io_memory; |
| 538 |
return; |
return; |
| 539 |
|
|
| 540 |
linux_boot = (kernel_filename != NULL); |
linux_boot = (kernel_filename != NULL); |
| 541 |
|
|
| 542 |
|
/* init CPUs */ |
| 543 |
|
|
| 544 |
|
env = cpu_init(); |
| 545 |
|
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
| 546 |
|
|
| 547 |
|
/* Register CPU as a 604 */ |
| 548 |
|
/* XXX: CPU model (or PVR) should be provided on command line */ |
| 549 |
|
// ppc_find_by_name("604r", &def); |
| 550 |
|
// ppc_find_by_name("604e", &def); |
| 551 |
|
ppc_find_by_name("604", &def); |
| 552 |
|
if (def == NULL) { |
| 553 |
|
cpu_abort(env, "Unable to find PowerPC CPU definition\n"); |
| 554 |
|
} |
| 555 |
|
cpu_ppc_register(env, def); |
| 556 |
|
/* Set time-base frequency to 100 Mhz */ |
| 557 |
|
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 558 |
|
|
| 559 |
/* allocate RAM */ |
/* allocate RAM */ |
| 560 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
| 602 |
initrd_size = 0; |
initrd_size = 0; |
| 603 |
} |
} |
| 604 |
|
|
|
/* Register CPU as a 604 */ |
|
|
/* XXX: CPU model (or PVR) should be provided on command line */ |
|
|
// ppc_find_by_name("604r", &def); |
|
|
// ppc_find_by_name("604e", &def); |
|
|
ppc_find_by_name("604", &def); |
|
|
if (def == NULL) { |
|
|
cpu_abort(cpu_single_env, "Unable to find PowerPC CPU definition\n"); |
|
|
} |
|
|
cpu_ppc_register(cpu_single_env, def); |
|
|
/* Set time-base frequency to 100 Mhz */ |
|
|
cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL); |
|
|
|
|
| 605 |
isa_mem_base = 0xc0000000; |
isa_mem_base = 0xc0000000; |
| 606 |
pci_bus = pci_prep_init(); |
pci_bus = pci_prep_init(); |
| 607 |
// pci_bus = i440fx_init(); |
// pci_bus = i440fx_init(); |
| 615 |
vga_ram_size, 0, 0); |
vga_ram_size, 0, 0); |
| 616 |
rtc_init(0x70, 8); |
rtc_init(0x70, 8); |
| 617 |
// openpic = openpic_init(0x00000000, 0xF0000000, 1); |
// openpic = openpic_init(0x00000000, 0xF0000000, 1); |
| 618 |
isa_pic = pic_init(pic_irq_request, cpu_single_env); |
isa_pic = pic_init(pic_irq_request, first_cpu); |
| 619 |
// pit = pit_init(0x40, 0); |
// pit = pit_init(0x40, 0); |
| 620 |
|
|
| 621 |
serial_init(0x3f8, 4, serial_hds[0]); |
serial_init(0x3f8, 4, serial_hds[0]); |