| 113 |
saddr = (addr & INTCTLM_MAXADDR) >> 2; |
saddr = (addr & INTCTLM_MAXADDR) >> 2; |
| 114 |
switch (saddr) { |
switch (saddr) { |
| 115 |
case 0: |
case 0: |
| 116 |
return s->intregm_pending; |
return s->intregm_pending & 0x7fffffff; |
| 117 |
case 1: |
case 1: |
| 118 |
return s->intregm_disabled; |
return s->intregm_disabled; |
| 119 |
case 4: |
case 4: |
| 132 |
saddr = (addr & INTCTLM_MAXADDR) >> 2; |
saddr = (addr & INTCTLM_MAXADDR) >> 2; |
| 133 |
switch (saddr) { |
switch (saddr) { |
| 134 |
case 2: // clear (enable) |
case 2: // clear (enable) |
| 135 |
// Force unused bits |
// Force clear unused bits |
| 136 |
val |= 0x7fb2007f; |
val &= ~0x7fb2007f; |
| 137 |
s->intregm_disabled &= ~val; |
s->intregm_disabled &= ~val; |
| 138 |
break; |
break; |
| 139 |
case 3: // set (disable, clear pending) |
case 3: // set (disable, clear pending) |
| 140 |
// Force unused bits |
// Force clear unused bits |
| 141 |
val &= ~0x7fb2007f; |
val &= ~0x7fb2007f; |
| 142 |
s->intregm_disabled |= val; |
s->intregm_disabled |= val; |
| 143 |
s->intregm_pending &= ~val; |
s->intregm_pending &= ~val; |
| 269 |
for (i = 0; i < MAX_CPUS; i++) { |
for (i = 0; i < MAX_CPUS; i++) { |
| 270 |
s->intreg_pending[i] = 0; |
s->intreg_pending[i] = 0; |
| 271 |
} |
} |
| 272 |
s->intregm_disabled = 0xffffffff; |
s->intregm_disabled = ~0xffb2007f; |
| 273 |
s->intregm_pending = 0; |
s->intregm_pending = 0; |
| 274 |
s->target_cpu = 0; |
s->target_cpu = 0; |
| 275 |
} |
} |