/[qemu]/qemu/hw/sun4m.c
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Diff of /qemu/hw/sun4m.c

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revision 1.11 by bellard, Mon Nov 21 23:29:55 2005 UTC revision 1.12 by bellard, Mon Dec 5 20:31:52 2005 UTC
# Line 56  Line 56 
56  #define PHYS_JJ_FDC     0x71400000      /* Floppy */  #define PHYS_JJ_FDC     0x71400000      /* Floppy */
57  #define PHYS_JJ_FLOPPY_IRQ 22  #define PHYS_JJ_FLOPPY_IRQ 22
58  #define PHYS_JJ_ME_IRQ 30               /* Module error, power fail */  #define PHYS_JJ_ME_IRQ 30               /* Module error, power fail */
59    #define MAX_CPUS 16
60    
61  /* TSC handling */  /* TSC handling */
62    
# Line 128  static void nvram_init(m48t59_t *nvram, Line 129  static void nvram_init(m48t59_t *nvram,
129      nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);      nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
130      nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */      nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */
131      // NVRAM_size, arch not applicable      // NVRAM_size, arch not applicable
132        m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
133        m48t59_write(nvram, 0x2E, 0);
134      m48t59_write(nvram, 0x2F, nographic & 0xff);      m48t59_write(nvram, 0x2F, nographic & 0xff);
135      nvram_set_lword(nvram,  0x30, RAM_size);      nvram_set_lword(nvram,  0x30, RAM_size);
136      m48t59_write(nvram, 0x34, boot_device & 0xff);      m48t59_write(nvram, 0x34, boot_device & 0xff);
# Line 179  void pic_set_irq(int irq, int level) Line 182  void pic_set_irq(int irq, int level)
182      slavio_pic_set_irq(slavio_intctl, irq, level);      slavio_pic_set_irq(slavio_intctl, irq, level);
183  }  }
184    
185    void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
186    {
187        slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
188    }
189    
190  static void *tcx;  static void *tcx;
191    
192  void vga_update_display()  void vga_update_display()
# Line 222  static void sun4m_init(int ram_size, int Line 230  static void sun4m_init(int ram_size, int
230                         const char *kernel_filename, const char *kernel_cmdline,                         const char *kernel_filename, const char *kernel_cmdline,
231                         const char *initrd_filename)                         const char *initrd_filename)
232  {  {
233      CPUState *env;      CPUState *env, *envs[MAX_CPUS];
234      char buf[1024];      char buf[1024];
235      int ret, linux_boot;      int ret, linux_boot;
236      unsigned int i;      unsigned int i;
# Line 230  static void sun4m_init(int ram_size, int Line 238  static void sun4m_init(int ram_size, int
238    
239      linux_boot = (kernel_filename != NULL);      linux_boot = (kernel_filename != NULL);
240    
241      env = cpu_init();      /* init CPUs */
242      register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);      for(i = 0; i < smp_cpus; i++) {
243      qemu_register_reset(main_cpu_reset, env);          env = cpu_init();
244            envs[i] = env;
245            if (i != 0)
246                env->halted = 1;
247            register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
248            qemu_register_reset(main_cpu_reset, env);
249        }
250      /* allocate RAM */      /* allocate RAM */
251      cpu_register_physical_memory(0, ram_size, 0);      cpu_register_physical_memory(0, ram_size, 0);
252    
253      iommu = iommu_init(PHYS_JJ_IOMMU);      iommu = iommu_init(PHYS_JJ_IOMMU);
254      slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);      slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
255        for(i = 0; i < smp_cpus; i++) {
256            slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
257        }
258    
259      tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);      tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
260      lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);      lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
261      nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);      nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
262      slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);      for (i = 0; i < MAX_CPUS; i++) {
263            slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
264        }
265        slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
266      slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);      slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
267      // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device      // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
268      // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device      // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device

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  Added in v.1.12

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