| 41 |
|
|
| 42 |
#ifdef SOFTMMU_CODE_ACCESS |
#ifdef SOFTMMU_CODE_ACCESS |
| 43 |
#define READ_ACCESS_TYPE 2 |
#define READ_ACCESS_TYPE 2 |
| 44 |
|
#define ADDR_READ addr_code |
| 45 |
#else |
#else |
| 46 |
#define READ_ACCESS_TYPE 0 |
#define READ_ACCESS_TYPE 0 |
| 47 |
|
#define ADDR_READ addr_read |
| 48 |
#endif |
#endif |
| 49 |
|
|
| 50 |
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr, |
| 85 |
/* XXX: could done more in memory macro in a non portable way */ |
/* XXX: could done more in memory macro in a non portable way */ |
| 86 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 87 |
redo: |
redo: |
| 88 |
tlb_addr = env->tlb_read[is_user][index].address; |
tlb_addr = env->tlb_table[is_user][index].ADDR_READ; |
| 89 |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
| 90 |
physaddr = addr + env->tlb_read[is_user][index].addend; |
physaddr = addr + env->tlb_table[is_user][index].addend; |
| 91 |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
| 92 |
/* IO access */ |
/* IO access */ |
| 93 |
if ((addr & (DATA_SIZE - 1)) != 0) |
if ((addr & (DATA_SIZE - 1)) != 0) |
| 124 |
|
|
| 125 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 126 |
redo: |
redo: |
| 127 |
tlb_addr = env->tlb_read[is_user][index].address; |
tlb_addr = env->tlb_table[is_user][index].ADDR_READ; |
| 128 |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
| 129 |
physaddr = addr + env->tlb_read[is_user][index].addend; |
physaddr = addr + env->tlb_table[is_user][index].addend; |
| 130 |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
| 131 |
/* IO access */ |
/* IO access */ |
| 132 |
if ((addr & (DATA_SIZE - 1)) != 0) |
if ((addr & (DATA_SIZE - 1)) != 0) |
| 201 |
|
|
| 202 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 203 |
redo: |
redo: |
| 204 |
tlb_addr = env->tlb_write[is_user][index].address; |
tlb_addr = env->tlb_table[is_user][index].addr_write; |
| 205 |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
| 206 |
physaddr = addr + env->tlb_write[is_user][index].addend; |
physaddr = addr + env->tlb_table[is_user][index].addend; |
| 207 |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
| 208 |
/* IO access */ |
/* IO access */ |
| 209 |
if ((addr & (DATA_SIZE - 1)) != 0) |
if ((addr & (DATA_SIZE - 1)) != 0) |
| 239 |
|
|
| 240 |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); |
| 241 |
redo: |
redo: |
| 242 |
tlb_addr = env->tlb_write[is_user][index].address; |
tlb_addr = env->tlb_table[is_user][index].addr_write; |
| 243 |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { |
| 244 |
physaddr = addr + env->tlb_write[is_user][index].addend; |
physaddr = addr + env->tlb_table[is_user][index].addend; |
| 245 |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
if (tlb_addr & ~TARGET_PAGE_MASK) { |
| 246 |
/* IO access */ |
/* IO access */ |
| 247 |
if ((addr & (DATA_SIZE - 1)) != 0) |
if ((addr & (DATA_SIZE - 1)) != 0) |
| 278 |
#undef SUFFIX |
#undef SUFFIX |
| 279 |
#undef USUFFIX |
#undef USUFFIX |
| 280 |
#undef DATA_SIZE |
#undef DATA_SIZE |
| 281 |
|
#undef ADDR_READ |