/[qemu]/qemu/target-arm/cpu.h
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revision 1.6 by bellard, Mon Feb 7 23:10:07 2005 UTC revision 1.7 by bellard, Tue Feb 22 19:27:29 2005 UTC
# Line 29  Line 29 
29  #define EXCP_PREFETCH_ABORT  3  #define EXCP_PREFETCH_ABORT  3
30  #define EXCP_DATA_ABORT      4  #define EXCP_DATA_ABORT      4
31    
32    /* We currently assume float and double are IEEE single and double
33       precision respectively.
34       Doing runtime conversions is tricky because VFP registers may contain
35       integer values (eg. as the result of a FTOSI instruction).
36       A double precision register load/store must also load/store the
37       corresponding single precision pair, although it is undefined how
38       these overlap.  */
39    
40  typedef struct CPUARMState {  typedef struct CPUARMState {
41      uint32_t regs[16];      uint32_t regs[16];
42      uint32_t cpsr;      uint32_t cpsr;
# Line 50  typedef struct CPUARMState { Line 58  typedef struct CPUARMState {
58      int interrupt_request;      int interrupt_request;
59      struct TranslationBlock *current_tb;      struct TranslationBlock *current_tb;
60      int user_mode_only;      int user_mode_only;
61        uint32_t address;
62    
63      /* in order to avoid passing too many arguments to the memory      /* in order to avoid passing too many arguments to the memory
64         write helpers, we store some rarely used information in the CPU         write helpers, we store some rarely used information in the CPU
# Line 58  typedef struct CPUARMState { Line 67  typedef struct CPUARMState {
67                                     written */                                     written */
68      unsigned long mem_write_vaddr; /* target virtual addr at which the      unsigned long mem_write_vaddr; /* target virtual addr at which the
69                                        memory was written */                                        memory was written */
70        /* VFP coprocessor state.  */
71        struct {
72            union {
73                float s[32];
74                double d[16];
75            } regs;
76    
77            /* We store these fpcsr fields separately for convenience.  */
78            int vec_len;
79            int vec_stride;
80    
81            uint32_t fpscr;
82    
83            /* Temporary variables if we don't have spare fp regs.  */
84            float tmp0s, tmp1s;
85            double tmp0d, tmp1d;
86    
87        } vfp;
88    
89      /* user data */      /* user data */
90      void *opaque;      void *opaque;
91  } CPUARMState;  } CPUARMState;

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