| 424 |
gen_op_movl_T0_psr(); |
gen_op_movl_T0_psr(); |
| 425 |
gen_movl_reg_T0(s, rd); |
gen_movl_reg_T0(s, rd); |
| 426 |
} |
} |
| 427 |
|
break; |
| 428 |
case 0x1: |
case 0x1: |
| 429 |
if (op1 == 1) { |
if (op1 == 1) { |
| 430 |
/* branch/exchange thumb (bx). */ |
/* branch/exchange thumb (bx). */ |
| 1577 |
{ |
{ |
| 1578 |
return addr; |
return addr; |
| 1579 |
} |
} |
| 1580 |
|
|
| 1581 |
|
#if defined(CONFIG_USER_ONLY) |
| 1582 |
|
|
| 1583 |
|
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 1584 |
|
int is_user, int is_softmmu) |
| 1585 |
|
{ |
| 1586 |
|
env->cp15_6 = address; |
| 1587 |
|
if (rw == 2) { |
| 1588 |
|
env->exception_index = EXCP_PREFETCH_ABORT; |
| 1589 |
|
} else { |
| 1590 |
|
env->exception_index = EXCP_DATA_ABORT; |
| 1591 |
|
} |
| 1592 |
|
return 1; |
| 1593 |
|
} |
| 1594 |
|
|
| 1595 |
|
#else |
| 1596 |
|
|
| 1597 |
|
#error not implemented |
| 1598 |
|
|
| 1599 |
|
#endif |