| 116 |
#define ID_MASK 0x00200000 |
#define ID_MASK 0x00200000 |
| 117 |
|
|
| 118 |
/* hidden flags - used internally by qemu to represent additionnal cpu |
/* hidden flags - used internally by qemu to represent additionnal cpu |
| 119 |
states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid |
states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid |
| 120 |
using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring |
using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring |
| 121 |
with eflags. */ |
with eflags. */ |
| 122 |
/* current cpl */ |
/* current cpl */ |
| 141 |
#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
| 142 |
#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
| 143 |
#define HF_VM_SHIFT 17 /* must be same as eflags */ |
#define HF_VM_SHIFT 17 /* must be same as eflags */ |
| 144 |
|
#define HF_HALTED_SHIFT 18 /* CPU halted */ |
| 145 |
|
|
| 146 |
#define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
#define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
| 147 |
#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
| 157 |
#define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
#define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
| 158 |
#define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
#define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
| 159 |
#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
| 160 |
|
#define HF_HALTED_MASK (1 << HF_HALTED_SHIFT) |
| 161 |
|
|
| 162 |
#define CR0_PE_MASK (1 << 0) |
#define CR0_PE_MASK (1 << 0) |
| 163 |
#define CR0_MP_MASK (1 << 1) |
#define CR0_MP_MASK (1 << 1) |