| 60 |
int cpl; |
int cpl; |
| 61 |
int iopl; |
int iopl; |
| 62 |
int tf; /* TF cpu flag */ |
int tf; /* TF cpu flag */ |
| 63 |
|
int singlestep_enabled; /* "hardware" single step enabled */ |
| 64 |
int jmp_opt; /* use direct block chaining for direct jumps */ |
int jmp_opt; /* use direct block chaining for direct jumps */ |
| 65 |
int mem_index; /* select memory access functions */ |
int mem_index; /* select memory access functions */ |
| 66 |
struct TranslationBlock *tb; |
struct TranslationBlock *tb; |
| 1713 |
{ |
{ |
| 1714 |
if (s->cc_op != CC_OP_DYNAMIC) |
if (s->cc_op != CC_OP_DYNAMIC) |
| 1715 |
gen_op_set_cc_op(s->cc_op); |
gen_op_set_cc_op(s->cc_op); |
| 1716 |
if (s->tf) { |
if (s->singlestep_enabled) { |
| 1717 |
|
gen_op_debug(); |
| 1718 |
|
} else if (s->tf) { |
| 1719 |
gen_op_raise_exception(EXCP01_SSTP); |
gen_op_raise_exception(EXCP01_SSTP); |
| 1720 |
} else { |
} else { |
| 1721 |
gen_op_movl_T0_0(); |
gen_op_movl_T0_0(); |
| 4371 |
dc->cpl = (flags >> HF_CPL_SHIFT) & 3; |
dc->cpl = (flags >> HF_CPL_SHIFT) & 3; |
| 4372 |
dc->iopl = (flags >> IOPL_SHIFT) & 3; |
dc->iopl = (flags >> IOPL_SHIFT) & 3; |
| 4373 |
dc->tf = (flags >> TF_SHIFT) & 1; |
dc->tf = (flags >> TF_SHIFT) & 1; |
| 4374 |
|
dc->singlestep_enabled = env->singlestep_enabled; |
| 4375 |
dc->cc_op = CC_OP_DYNAMIC; |
dc->cc_op = CC_OP_DYNAMIC; |
| 4376 |
dc->cs_base = cs_base; |
dc->cs_base = cs_base; |
| 4377 |
dc->tb = tb; |
dc->tb = tb; |
| 4429 |
break; |
break; |
| 4430 |
/* if single step mode, we generate only one instruction and |
/* if single step mode, we generate only one instruction and |
| 4431 |
generate an exception */ |
generate an exception */ |
| 4432 |
if (dc->tf) { |
if (dc->tf || dc->singlestep_enabled) { |
| 4433 |
gen_op_jmp_im(pc_ptr - dc->cs_base); |
gen_op_jmp_im(pc_ptr - dc->cs_base); |
| 4434 |
gen_eob(dc); |
gen_eob(dc); |
| 4435 |
break; |
break; |