| 1897 |
#else |
#else |
| 1898 |
gen_op_xor_T1_T0(); |
gen_op_xor_T1_T0(); |
| 1899 |
gen_op_wrpsr(); |
gen_op_wrpsr(); |
| 1900 |
|
save_state(dc); |
| 1901 |
|
gen_op_next_insn(); |
| 1902 |
|
gen_op_movl_T0_0(); |
| 1903 |
|
gen_op_exit_tb(); |
| 1904 |
|
dc->is_br = 1; |
| 1905 |
#endif |
#endif |
| 1906 |
} |
} |
| 1907 |
break; |
break; |
| 2348 |
gen_op_store_FT0_fpr(rd); |
gen_op_store_FT0_fpr(rd); |
| 2349 |
break; |
break; |
| 2350 |
case 0x21: /* load fsr */ |
case 0x21: /* load fsr */ |
| 2351 |
|
gen_op_ldst(ldf); |
| 2352 |
gen_op_ldfsr(); |
gen_op_ldfsr(); |
|
gen_op_store_FT0_fpr(rd); |
|
| 2353 |
break; |
break; |
| 2354 |
case 0x22: /* load quad fpreg */ |
case 0x22: /* load quad fpreg */ |
| 2355 |
goto nfpu_insn; |
goto nfpu_insn; |
| 2431 |
gen_op_ldst(stf); |
gen_op_ldst(stf); |
| 2432 |
break; |
break; |
| 2433 |
case 0x25: /* stfsr, V9 stxfsr */ |
case 0x25: /* stfsr, V9 stxfsr */ |
|
gen_op_load_fpr_FT0(rd); |
|
|
// XXX |
|
| 2434 |
gen_op_stfsr(); |
gen_op_stfsr(); |
| 2435 |
|
gen_op_ldst(stf); |
| 2436 |
break; |
break; |
| 2437 |
case 0x26: /* stdfq */ |
case 0x26: /* stdfq */ |
| 2438 |
goto nfpu_insn; |
goto nfpu_insn; |